MB87L2250 Ver la hoja de datos (PDF) - Fujitsu

Número de pieza

componentes Descripción

Fabricante

MB87L2250

MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU

Fujitsu 

Product Profile

October 1998

Edition 1.1

MB87L2250 - MPEG2 Decoder

1. Chip Architecture

Figure 1 shows the chip architecture of Demultiplexer and Audio/Video Decoder MB87L2250, which is dedicated

for DVB compliant applications (DVB-S, DVB-C, DVB-T).

Demodulation

Module

SDRAM

PROM

CE, EE, Flash

CPU

SparcLite

(optional)

DVB

Descrambler

Transport

Demultiplexer)

MPEG

Video

Graphics/Video

Controller

(OSD, Teletext)

MPEG

Audio

PAL / NTSC

Encoder

Audio DAC

ARC

32 Bit

RISC CPU

Host

Interface

(optional)

MB87L2250

SDRAM Interface

1 KByte

Instruction

Cache

APLL

I²C

Interface

IC Card

Interface A/B

CLK81

CLK54

CLK27

IR

Receiver

SDRAM

(16 MBit,

81MHz)

Figure 1: Block Diagram

2

Fujitsu Mikroelektronik GmbH Proprietary Information

Confidential

Share Link: