MAX19708ETM Ver la hoja de datos (PDF) - Maxim Integrated
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componentes Descripción
Fabricante
MAX19708ETM Datasheet PDF : 37 Pages
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10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, TA = +25°C, unless otherwise noted.)
AUX-ADC INTEGRAL NONLINEARITY
2.0
AUX-ADC DIFFERENTIAL NONLINEARITY
0.8
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
3.0
1.5
2.5
1.0
0.4
2.0
0.5
0
0
1.5
-0.5
1.0
-1.0
-0.4
0.5
-1.5
-2.0
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
-0.8
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
0
0.001 0.01 0.1
1
10 100
OUTPUT SOURCE CURRENT (mA)
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
3.0
2.5
AUX-DAC SETTLING TIME
STEP FROM 1/4FS TO 3/4FS
2.0
1.5
500mV/div
1.0
0.5
0
0.001 0.01 0.1
1
10 100
OUTPUT SINK CURRENT (mA)
500ns/div
PIN
1
2, 8, 11, 31,
33, 39, 43
3
4
5, 7, 12, 32, 42
6
9
NAME
REFP
VDD
IAP
IAN
GND
CLK
QAN
Pin Description
FUNCTION
Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with
a 0.1µF capacitor.
Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.
Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
Analog Ground. Connect all GND pins to ground plane.
Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.
Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
14 ______________________________________________________________________________________
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