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MAX19708ETM

10-Bit, 11Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

10-Bit, 11Msps, Ultra-Low-Power

Analog Front-End

5.5 CLOCK-CYCLE LATENCY (CHQ)

5 CLOCK-CYCLE LATENCY (CHI)

CHI

CHQ

CLK

tCLK

tCL

tCH

tDOQ

D0–D9

tDOI

D0Q

D1I

D1Q

D2I

D2Q

D3I

D3Q

D4I

D4Q

D5I

D5Q

D6I

D6Q

Figure 3. Rx ADC System Timing Diagram

Table 2. Tx Path Output Voltage vs. Input Codes

(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = 410 for 820mVP-P

Full Scale and VFS = 500 for 1VP-P Full Scale)

DIFFERENTIAL OUTPUT VOLTAGE (V)

OFFSET BINARY (D0–D9)

INPUT DECIMAL CODE

( ) VFS

VREFDAC

1024

× 1023

1023

11 1111 1111

1023

( ) VFS

VREFDAC

1024

× 1021

1023

11 1111 1110

1022

( ) VFS

VREFDAC

1024

×3

1023

10 0000 0001

513

( ) VFS

VREFDAC

1024

×1

1023

10 0000 0000

512

( ) VFS

−VREFDAC × 1

1024 1023

01 1111 1111

511

( ) VFS

−VREFDAC × 1021

1024 1023

00 0000 0001

1

( ) VFS

−VREFDAC × 1023

1024 1023

00 0000 0000

0

Dual 10-Bit Tx DAC and Transmit Path

The dual 10-bit digital-to-analog converters (Tx DAC)

operate with clock speeds up to 11MHz. The Tx DAC

digital inputs, D0–D9, are multiplexed on a single 10-bit

bus. The voltage reference determines the Tx path full-

scale voltage at IDP, IDN and QDP, QDN analog out-

puts. See the Reference Configurations section for

setting reference voltage. Each Tx path output channel

integrates a lowpass filter tuned to meet the TD-SCDMA

spectral mask requirements.

The TD-SCDMA filters are tuned for 1.32MHz cutoff fre-

quency and > 55dB image rejection at fIMAGE =

4.32MHz, fOUT = 800kHz, and fCLK = 5.12MHz. See

Figure 4 for an illustration of the filter frequency response.

Buffer amplifiers follow the TD-SCDMA filters. The amplifi-

er outputs (IDN, IDP, QDN, QDP) are biased at an

adjustable common-mode DC level and designed to

drive a differential input stage with ≥ 70kΩ input imped-

ance. This simplifies the analog interface between RF

18 ______________________________________________________________________________________

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