55LD019A-45-C-MVWE Ver la hoja de datos (PDF) - Silicon Storage Technology
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55LD019A-45-C-MVWE Datasheet PDF : 79 Pages
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ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
Data Sheet
CS1FX#/CS3FX#
DMARQ
T0
TN
DMACK#
TK
TD
TJ
IORD#/IOWR
TE
TZ
Read DQ15-0
TG
TF
TH
Write DQ15-0
Note: 1. To terminate the transmission of a data burst, the host should negate DMACK# within the
specified time after a IORD# or IOWR# pulse. No further IORD# or IOWR# pulses shall be
asserted for this burst.
2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted
and wait for the host to reassert DMACK# or may negate DMARQ at any time after detecting
that DMACK# has been negated.
1241 F08.0
FIGURE 12-7: Host Terminates a Multi-word DMA Data Transfer
12.2.4 Media Side Interface I/O Timing Specifications
TABLE 12-12: SST55LD019A/B/C Timing Parameters
Symbol
TCLS
TCLH
TCS
TCH
TCHR
TWP
TWH
TWC
TALS
TALH
TDS
TDH
TRP
TRR
TREA
TRC
TREH
TRHZ
Parameter
FCLE Setup Time
FCLE Hold Time
FCE# Setup Time
FCE# Hold Time for Command/Data Write Cycle
FCE# Hold Time for Sequential Read Last Cycle
FWE# Pulse Width
FWE# High Hold Time
Write Cycle Time
FALE Setup Time
FALE Hold Time
FAD[15:0] Setup Time
FAD[15:0] Hold Time
FRE# Pulse Width
Ready to FRE# Low
FRE# Data Setup Access Time
Read Cycle Time
FRE# High Hold Time
FRE# High to Data Hi-Z
Note: All AC specifications are guaranteed by design.
Min
Max
Units
20
-
ns
40
-
ns
40
-
ns
40
-
ns
-
40
ns
20
-
ns
20
-
ns
40
-
ns
20
-
ns
40
-
ns
20
-
ns
20
-
ns
20
-
ns
40
-
ns
20
-
ns
40
-
ns
30
-
ns
5
-
ns
T12-12.0 1241
©2006 Silicon Storage Technology, Inc.
71
S71241-04-000
12/06
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