AD5694RARUZ Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5694RARUZ Datasheet PDF : 32 Pages
| |||
AD5696R/AD5695R/AD5694R
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1
Table 4.
Parameter2
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
t12
t13
CB4
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1CB4
20
400
Max
0.9
300
300
400
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
pF
Conditions/Comments
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SDA and SCL when transmitting/ receiving
LDAC pulse width
SCL rising edge to LDAC rising edge
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
START
CONDITION
SDA
SCL
t9
t3
t4
t10
t6
LDAC1
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
REPEATED START
CONDITION
t11
t4
t2
t5
t1
t7
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8
t12
Rev. 0 | Page 6 of 32
Share Link: 