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P3041NSE7PNC

P3041 QorIQ Integrated Processor Hardware Specifications

Freescale Semiconductor 

Security Fuse Processor

6. Parallelism measurement excludes any effect of mark on the top surface of package.

Figure 63. Mechanical Dimensions of the FC-PBGA with Full Lid

5 Security Fuse Processor

This chip implements the QorIQ platform’s trust architecture, supporting capabilities such as secure boot. Use of the Trust

Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust

Architecture and SFP can be found in the chip reference manual.

In order to program SFP fuses, the user is required to supply 1.5 V to the POVDD pin per Section 2.2, “Power-Up Sequencing.”

POVDD should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse

programming cycles. All other times POVDD must be connected to GND. The sequencing requirements for raising and lowering

POVDD are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the recommended fuse

programming temperature range per Table 3.

Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect

POVDD to GND.

6 Ordering Information

Please contact your local Freescale sales office or regional marketing team for ordering information.

6.1 Part Numbering Nomenclature

This table provides the Freescale QorIQ platform part numbering nomenclature.Not all possible combinations of part numbers

implied by the part numbering scheme are supported. For a list of available part numbers, please contact your Freescale Sales

office. Each part number also contains a revision code which refers to the die mask revision number.

Table 114. Part Numbering Nomenclature

p

n

nn

n

x

t

e

n

c

d

r

Generation Platform

Number

of Cores

Derivative

Qual

Status

Temperature

Range

Encryption

Package

Type

CPU

DDR

Die

Freq Data Rate Revision

P = 45 nm 1–5 01 = 1 core

02 = 2 core

04 = 4 core

0–9

P=

S=

E = SEC

1=

M=

M=

A=

Prototype Std temp

present FC-PBGA 1200 MHz 1200 MT/s Rev 1.0

N=

X=

N = SEC not Pb-free

N=

N=

B=

Industrial Extended

present spheres 1333 MHz 1333 MT/s Rev 1.1

qualification temp (–40 to

7=

P=

C=

105 C)

FC-PBGA 1500 MHz

Rev 2.0

C4 and

sphere

Pb-free

P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2

156

Freescale Semiconductor

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