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AD7896JR

2.7 V to 5.5 V, 12-Bit, 8 μ
s ADC in 8-Lead SOIC/PDIP

Analog Devices 

AD7896

To chip select the AD7896 in systems where more than one

device is connected to the 8X51/L51 serial port, a port bit,

configured as an output, from one of the 8X51/L51 parallel

ports can be used to gate on or off the serial clock to the AD7896.

A simple AND function on this port bit and the serial clock from

the 8X51/L51 will provide this function. The port bit should be

high to select the AD7896 and low when it is not selected.

The end of conversion is monitored by using the BUSY signal,

which is shown in the interface diagram of Figure 5, with the

BUSY line from the AD7896 connected to the Port P1.2 of the

8X51/L51 so the BUSY line can be polled by the 8X51/L51.

The BUSY line can be connected to the INT1 line of the

8X51/L51 if an interrupt driven system is preferred. These two

options are shown on the diagram.

Note also that the AD7896 outputs the MSB first during a read

operation while the 8X51/L51 expects the LSB first. Therefore,

the data that is read into the serial buffer needs to be rearranged

before the correct data format from the AD7896 appears in the

accumulator.

The serial clock rate from the 8X51/L51 is limited to signifi-

cantly less than the allowable input serial clock frequency with

which the AD7896 can operate. As a result, the time to read

data from the part will actually be longer than the conversion

time of the part. This means that the AD7896 cannot run at its

maximum throughput rate when used with the 8X51/L51.

The BUSY line can be connected to the IRQ line of the

68HC11/L11 if an interrupt driven system is preferred. These

two options are shown in the diagram.

The serial clock rate from the 68HC11/L11 is limited to signifi-

cantly less than the allowable input serial clock frequency with

which the AD7896 can operate. As a result, the time to read

data from the part will actually be longer than the conversion

time of the part. This means that the AD7896 cannot run at its

maximum throughput rate when used with the 68HC11/L11.

PC2 OR

IRQ

68HC11/L11

SCK

BUSY

AD7896

SCLK

MISO

SDATA

Figure 6. AD7896 to 68HC11/L11 Interface

AD7896–ADSP-2105 Interface

P1.2

OR

INT1

8X51/L51

P3.0

BUSY

AD7896

SDATA

P3.1

SCLK

Figure 5. AD7896 to 8X51/L51 Interface

AD7896–68HC11/L11 Interface

An interface circuit between the AD7896 and the 68HC11/L11

microcontroller is shown in Figure 6. For the interface shown,

the 68HC11/L11 SPI port is used and the 68HC11/L11 is con-

figured in its single-chip mode. The 68HC11/L11 is configured

in the master mode with its CPOL bit set to a Logic 0 and its

CPHA bit set to a Logic 1. As with the previous interface, the

diagram shows the simplest form of the interface, where the

AD7896 is the only part connected to the serial port of the

68HC11/L11 and, therefore, no decoding of the serial read

operations is required.

Once again, to chip select the AD7896 in systems where more

than one device is connected to the 68HC11/L11 serial port, a

port bit, configured as an output, from one of the 68HC11/L11

parallel ports can be used to gate on or off the serial clock to the

AD7896. A simple AND function on this port bit and the serial

clock from the 68HC11/L11 will provide this function. The port

bit should be high to select the AD7896 and low when it is

not selected.

The end of conversion is monitored by using the BUSY signal

which is shown in the interface diagram of Figure 6. With the

BUSY line from the AD7896 connected to the Port PC2 of the

68HC11/L11, the BUSY line can be polled by the 68HC11/L11.

–10–

Rev. D

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