74ALS164 Ver la hoja de datos (PDF) - Philips Electronics
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74ALS164 Datasheet PDF : 9 Pages
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Philips Semiconductors
8-bit serial-in parallel-out shift register
Product specification
74ALS164
FEATURES
• Gated serial data inputs
• Typical shift frequency of 75MHz
• Asynchronous master reset
• Buffered clock and data inputs
• Fully synchronous data transfer
DESCRIPTION
The 74ALS164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is
entered serially through one of two inputs (Dsa, Dsb); either input
can be used as an active-high enable for data entry through the
other input. Both inputs must be connected together or an unused
input must be tied High.
Data shifts one place to the right on each Low-to-high transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all outputs
Low.
PIN CONFIGURATION
Dsa 1
Dsb 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
14 VCC
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
8 CP
SF00717
TYPE
74ALS164
TYPICAL
fMAX
75MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
10mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
14-pin plastic DIP
74ALS164N
14-pin plastic SO
74ALS164D
DRAWING
NUMBER
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
Dsa, Dsb
Data inputs
1.0/1.0
CP
Clock Pulse input (active rising edge)
1.0/1.0
MR
Master Reset input (active-Low)
1.0/1.0
Q0 – Q7
Data outputs
20/80
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
2
8
CP
Dsa Dsb
9
MR
Q0 Q1 Q3 Q4 Q0 Q1 Q3 Q4
SRG8
8
C1/→
9
R
1
&
2
1D
3 4 5 6 10 11 12 13
VCC = Pin 14
GND = Pin 7
SF00713
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
3
4
5
6
10
11
12
13
SF00714
1991 Feb 08
2
853–1510 01670
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