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74LV165A Datasheet PDF : 19 Pages
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NXP Semiconductors
74LV165A
8-bit parallel-in/serial-out shift register
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Conditions
CPD
power
dissipation
VI = GND to VCC; VCC = 3.3 V
capacitance
Tamb = 40 C to +85 C
Min
Typ[1]
Max
[6] -
24
-
Unit
pF
[1] Typical values are measured at Tamb = 25 °C and nominal VCC.
[2] tpd is the same as tPHL and tPLH.
[3] Typical values are measured at VCC = 2.5 V.
[4] Typical values are measured at VCC = 3.3 V.
[5] Typical values are measured at VCC = 5.0 V.
[6] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
9,
&3&(LQSXW
*1'
92+
4RU4RXWSXW
92/
IPD[
90
W:
W3+/
90
W3/+
DDD
Fig 7.
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and
maximum clock frequency
74LV165A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 28 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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