74LVC1G10 Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
Fabricante
74LVC1G10 Datasheet PDF : 14 Pages
| |||
NXP Semiconductors
74LVC1G10
Single 3-input NAND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tpd
propagation delay A, B and C to Y; see Figure 7 [2]
VCC = 1.65 V to 1.95 V
1.5
4.7 18.0
VCC = 2.3 V to 2.7 V
1.0
3.0
6.5
VCC = 2.7 V
1.0
3.0
6.0
VCC = 3.0 V to 3.6 V
1.0
2.6
5.0
VCC = 4.5 V to 5.5 V
1.0
1.9
3.6
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V [3]
-
12
-
capacitance
−40 °C to +125 °C Unit
Min
Max
1.5
21.5 ns
1.0
7.8 ns
1.0
7.5 ns
1.0
6.2 ns
1.0
4.4 ns
-
- pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
VI
A, B, C,
input
GND
VOH
Y output
VOL
VM
tPLH
VM
tPHL
001aag692
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (A, B, C) to output (Y) propagation delays
74LVC1G10_1
Product data sheet
Rev. 01 — 2 October 2007
© NXP B.V. 2007. All rights reserved.
6 of 14
Share Link: 