A3959 Ver la hoja de datos (PDF) - Allegro MicroSystems

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componentes Descripción

Fabricante

A3959

DMOS Full-Bridge PWM Motor Driver

Allegro MicroSystems 

A3959

DMOS Full-Bridge PWM Motor Driver

Package B (DIP)

Package LB (SOIC)

Package LP (TSSOP)

CP2 1

CP1 2

CHARGE PUMP

PHASE

ıθ

3

24 CP

23 VREG

22 SLEEP

ROSC 4

GROUND 5

GROUND 6

21 OUTB

VBB

20

LOAD

SUPPLY

19 GROUND

GROUND 7

18 GROUND

GROUND 8

LOGIC

SUPPLY

99 VDD

ENABLE 10

PFD2 11

÷10

BLANK 12

PWM TIMER

17 SENSE

16 OUTA

15 EXT MODE

14 REF

13 PFD1

Dwg. PP-069-5A

Terminal List

CP 1

CP2 2

CP1 3

PHASE

Q

4

ROSC 5

GROUND 6

GROUND 7

LOGIC SUPPLY 8 VDD

ENABLE 9

PFD2 10

BLANK 11

PFD1 12

24 VREG

23 SLEEP

NC 22

NO

CONNECTION

21 OUTB

VBB 20 LOAD SUPPLY

19 GROUND

18 GROUND

17 SENSE

16 OUTA

NC

15

NO

CONNECTION

14 EXT MODE

÷10

13 REF

Dwg. PP-069-4

CP 1

CP2 2

CP1 3

NC 4

Q

PHASE 5

ROSC 6

GROUND 7

GROUND 8

LOGIC SUPPLY 9 VDD

ENABLE 10

NC 11

PFD2 12

BLANK 13

PFD1 14

28 GROUND

27 VREG

26 SLEEP

NC 25

NO

CONNECTION

24 OUTB

VBB 23 LOAD SUPPLY

22 NC

21 SENSE

20 NC

19 NC

18 OUTA

NC

17

NO

CONNECTION

16 EXT MODE

÷10

15 REF

Terminal Name

Terminal Description

B (DIP)

LB (SOIC)

LP (TSSOP)

CP

Reservoir capacitor (typically 0.22 μF)

24

1

1

CP1 & CP2

The charge pump capacitor (typically 0.22 μF)

1&2

2&3

2&3

NC

No (internal) connection

—

—

4

PHASE

Logic input for direction control

3

4

5

ROSC

Oscillator resistor

4

5

6

GROUND

Grounds

5, 6, 7, 8*

6, 7

7, 8*

LOGIC SUPPLY VDD, the low voltage (typically 5 V) supply

9

8

9

ENABLE

Logic input for enable control

10

9

10

NC

No (internal) connection

–

–

11

PFD2

Logic-level input for fast decay

11

10

12

BLANK

Logic-level input for blanking control

12

11

13

PFD1

Logic-level input for fast decay

13

12

14

REF

VREF, the load current reference input voltage

14

13

15

EXT MODE

Logic input for PWM mode control

15

14

16

NO CONNECT

No (Internal) connection

—

15

17

OUTA

One of two DMOS bridge outputs to the motor

16

16

18

NC

No (internal) connection

–

–

19, 20

SENSE

Sense resistor

17

17

21

NC

No (internal) connection

–

–

22

GROUND

Grounds

18, 19*

18, 19

—

LOAD SUPPLY

VBB, the high-current, 9.5 V to 50 V, motor supply

20

20

23

OUTB

One of two DMOS bridge outputs to the motor

21

21

24

NO CONNECT

No (Internal) connection

—

22

25

SLEEP

Logic-level Input for sleep operation

22

23

26

VREG

Regulator decoupling capacitor (typically 0.22 μF)

23

24

27

GROUND

Ground

—

—

28*

* For the B (DIP) package only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5

and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the LP (TSSOP) package, the grounds at terminals 7, 8, and 28

should be connected together at the exposed pad beneath the device.

Allegro MicroSystems, Inc.

9

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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