ACS8595 Ver la hoja de datos (PDF) - Semtech Corporation
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ACS8595 Datasheet PDF : 12 Pages
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ACS8595 ATCA
ADVANCED COMMUNICATIONS
Register Map
FINAL
PRODUCT BRIEF
Table 7 Register Map
Register Name
Data Bit
RO = Read Only
R/W = Read/Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
chip_id (RO)
00 4D
chip_id[7:0], 8 LSBs of Chip ID
01 21
chip_id[15:8], 8 MSBs of Chip ID
chip_revision (RO)
02 00
chip_revision[7:0]
test_register1 (R/W)
03 14 Phase_alarm Disable_180
Resync_
analog
Set to 0
8K Edge
Polarity
Set to 0
Set to 0
test_register2 (R/W)
04 12
Do not use
sts_interrupts (R/W)
05 FF
status_SEC2_ status_SEC1_ status_SEC2_ status_SEC1_
DIFF
DIFF
TTL
TTL
06 3F operating_
mode
DPLL1_main_
ref_failed
status_SEC3
sts_current_DPLL_frequency,
see OC/OD
07 00
Bits [18:16] of sts_current_DPLL_frequency
sts_interrupts (R/W)
08 10 Sync_alarm_
int
sts_operating_mode (RO)
09 01 Sync_alarm
DPLL2_Lock DPLL1_freq_ DPLL2_freq_
soft_alarm
soft_alarm
DPLL1_operating_mode
sts_priority_table (RO)
0A 00
Highest priority validated source
Currently selected source
0B 00
3rd highest priority validated source
2nd highest priority validated source
sts_current_DPLL_frequency [7:0] 0C 00
Bits [7:0] of sts_current_DPLL_frequency
(RO)
[15:8] 0D 00
Bits [15:8] of sts_current_DPLL_frequencyy
[18:16] 07 00
Bits [18:16] of sts_current_DPLL_frequency
sts_sources_valid (RO)
0E 00
SEC2 DIFF
SEC1 DIFF
SEC2 TTL
SEC1 TTL
0F 00
SEC3
sts_reference_sources (RO)
Alarm Status on inputs:
SEC1 & SEC2 TTL 11 22
No Activity
SEC2 TTL
Phase Lock
SEC2 TTL
No Activity
SEC1 TTL
Phase Lock
SEC1 TTL
SEC1 & SEC2 DIFF 12 22
No Activity
SEC2 DIFF
Phase Lock
SEC2 DIFF
No Activity
SEC1 DIFF
Phase Lock
SEC1 DIFF
SEC3 14 22
No Activity
SEC3
Phase Lock
SEC3
cnfg_ref_selection_priority (R/W) 19 32
SEC1 & SEC2 TTL
programmed_priority_SEC2_TTL
programmed_priority_SEC1_TTL
SEC1 & SEC2 DIFF 1A 00
programmed_priority_SEC2_DIFF
programmed_priority_SEC1_DIFF
SEC3 1C 04
programmed_priority_SEC3
cnfg_ref_source_frequency_
<input> (R/W), where <input> =
SEC1 TTL 22 00 divn_SEC1 TTL lock8k_SEC1
TTL
Bucket_id_SEC1 TTL
reference_source_frequency_SEC1 TTL
SEC2 TTL 23 00 divn_SEC2 TTL lock8k_SEC2
TTL
Bucket_id_SEC2 TTL
reference_source_frequency_SEC2 TTL
SEC1 DIFF 24 03 divn_SEC1
DIFF
lock8k_SEC1
DIFF
Bucket_id_SEC1 DIFF
reference_source_frequency_SEC1 DIFF
SEC2 DIFF 25 03 divn_SEC2
DIFF
lock8k_SEC2
DIFF
Bucket_id_SEC2 DIFF
reference_source_frequency_SEC2 DIFF
SEC3 28 03 divn_SEC3
lock8k_SEC3
Bucket_id_SEC3
reference_source_frequency_SEC3
cnfg_operating_mode (R/W)
32 00
DPLL1_operating_mode
force_select_reference_source
(R/W)
33 0F
forced_select_SEC_input
cnfg_input_mode (R/W)
34 CA auto_extsync_ phalarm_
en
timeout
XO_ edge
extsync_en ip_sonsdhb
reversion_
mode
cnfg_DPLL2_path (R/W)
35 A0
DPLL2_dig_
feedback
cnfg_differential_inputs (R/W) 36 03
SEC2_DIFF_
PECL
SEC1_DIFF_
PECL
cnfg_dig_outputs_sonsdh (R/W) 38 04
dig2_sonsdh dig1_sonsdh
cnfg_digtial_frequencies (R/W) 39 08
digital2_frequency
digital1_frequency
cnfg_differential_output (R/W) 3A C2
Output O1 _LVDS_PECL
cnfg_auto_bw_sel
3B 98 auto_BW_sel
DPLL1_lim_int
Revision 2.00/October 2005 © Semtech Corp.
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