AD5801 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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AD5801 Datasheet PDF : 13 Pages
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AD5801
Preliminary Technical Data
Table 3. I2C Serial Interface
Parameter1
Limit at TMIN, TMAX
FSCL
400
t1
2.5
t2
0.6
t3
1.3
t4
0.6
t5
100
t62
0.9
0
t7
0.6
t8
0.6
t9
1.3
t10
300
0
t11
300
0
300
20 + 0.1 CB
CB3
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT data hold time
tHD, DAT data hold time
tSU, STA setup time for repeated start
tSU, STO stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, fall time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 See 2.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t10 t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t7
t1
REPEATED
START
CONDITION
Figure2.. I2C Interface Timing Diagram
Block Diagram
t8
STOP
CONDITION
Rev. 0 | Page 6 of 13
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