AD6654 Ver la hoja de datos (PDF) - Analog Devices
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AD6654 Datasheet PDF : 88 Pages
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AD6654
SERIAL PORT TIMING CHARACTERISTICS
Table 9.
Parameter1, 2, 3
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
SCLK Period
tSCLKL
SCLK Low Time
tSCLKH
SCLK High Time
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
tHSCS
SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI
SDI to ↑SCLK Setup Time
tHSDI
SDI to ↑SCLK Hold Time
tSSRFS
SRFS to ↓SCLK Setup Time
tHSRFS
SRFS to ↓SCLK Hold Time
tSSTFS
STFS to ↓SCLK Setup Time
tHSTFS
STFS to ↓SCLK Hold Time
tSSCS
SCS to ↑SCLK Setup Time
tHSCS
SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 SCLK rise/fall time should be 3 ns maximum.
Min
10.0
1.60
1.60
1.30
0.40
4.12
−2.78
4.28
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
Typ
0.5 × tSCLK
0.5 × tSCLK
Max Unit
ns
ns
ns
ns
ns
ns
ns
7.96 ns
ns
ns
ns
ns
ns
ns
ns
ns
7.95 ns
Rev. 0 | Page 11 of 88
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