AD7118CQ Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD7118CQ Datasheet PDF : 6 Pages
| |||
AD7118
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7118 consists of a 17-bit R-2R CMOS multiplying D/A
converter with extensive digital input logic. The logic translates
the 6-bit binary input into a 17-bit word which is used to drive
the D/A converter. Table I gives the nominal output voltages
(and levels relative to 0 dB = 10 V) for all possible input codes.
The transfer function for the circuit of Figure 1 is given by:
VO
=
−V
IN 10 exp −
1.5N
20
or VO = −1.5N
V IN dB
where N is the binary input for values 0 to 57. For 60 ≤ N ≤ 63
the output is zero. See note 3 at bottom of Table I.
The current source ILEAKAGE is composed of surface and junc-
tion leakages and as with most semiconductor devices, roughly
doubles every 10°C–see Figure 10. The resistor RO as shown in
Figure 3 is the equivalent output resistance of the device which
varies with input code (excluding all 0’s code) from 0.8R to
2R. R is typically 12 kΩ. COUT is the capacitance due to the
N-channel switches and varies from about 50 pF to 80 pF de-
pending upon the digital input. For further information on
CMOS multiplying D/A converters refer to “Application Guide
to CMOS Multiplying D/A Converters” which is available from
Analog Devices, Publication Number G479–15–8/78.
Figure 2. Simplified D/A Circuit of AD7118
Figure 1. Typical Circuit Configuration
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the D/A converter section
Figure 3. Equivalent Analog Output Circuit of AD7118
of the AD7118 and Figure 3 gives an approximate equivalent
circuit.
Table I. Ideal Attenuation vs. Input Code
Digital Input
N
D5 D0
00 00 00 00
01 00 00 01
02 00 00 10
03 00 00 11
04 00 01 00
05 00 01 01
06 00 01 10
07 00 01 11
08 00 10 00
09 00 10 01
10 00 10 10
11 00 10 11
12 00 11 00
13 00 11 01
14 00 11 10
15 00 11 11
16 01 00 00
17 01 00 01
18 01 00 10
19 01 00 11
20 01 01 00
21 01 01 01
22 01 01 10
23 01 01 11
24 01 10 00
25 01 10 01
26 01 10 10
27 01 10 11
28 01 11 00
29 01 11 01
30 01 11 10
Attenuation
dB
00.0
01.5
03.0
04.5
06.0
07.5
09.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
24.0
25.5
27.0
28.5
30.0
31.5
33.0
34.5
36.0
37.5
39.0
40.5
42.0
43.5
45.0
VOUT1
10.00
8.414
7.079
5.957
5.012
4.217
3.548
2.985
2.512
2.113
1.778
1.496
1.259
1.059
0.891
0.750
0.631
0.531
0.447
0.376
0.316
0.266
0.224
0.188
0.158
0.133
0.112
0.0944
0.0794
0.0668
0.0562
N
Digital Input
Attenuation VOUT1
31
01 11 11
46.5
32
10 00 00
48.0
0.0473
0.0398
33
10 00 01
49.5
0.0335
34
10 00 10
51.0
35
10 00 11
52.5
0.0282
0.0237
36
10 01 00
54.0
0.0200
37
10 01 01
55.5
38
10 01 10
57.0
0.0168
0.0141
39
10 01 11
58.5
0.0119
40
10 10 00
60.0
41
10 10 01
61.5
0.0100
0.00841
42
10 10 10
63.0
0.00708
43
10 10 11
64.5
44
10 11 00
66.0
0.00596
0.00501
45
10 11 01
67.5
0.00422
46
10 11 10
69.0
47
10 11 11
70.5
0.00355
0.00299
48
11 00 00
72.0
0.00251
49
11 00 01
73.5
50
11 00 10
75.0
0.00211
0.00178
51
11 00 11
76.5
0.00150
52
11 01 00
78.0
53
11 01 01
79.5
0.00126
0.00106
54
11 01 10
81.0
0.000891
55
11 01 11
82.5
0.000750
56
11 10 00
84.0
0.000631
57
11 10 01
85.5
0.000531
58
11 10 10
87.0
59
11 10 11
88.5
60
11 11 XX2
∞
0.000447
0.000376
NOTES
1VIN = –10 V dc
2X = 1 or 0. Output is fully muted for N ≥ 60
3Monotonic operation is not guaranteed for N = 58, 59
–4–
REV. A
Share Link: 