AD7233AN Ver la hoja de datos (PDF) - Analog Devices
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AD7233AN Datasheet PDF : 8 Pages
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AD7233–SPECIFICATIONS1 (VDD = +12 V to +15 V,2 VSS = –12 V to –15 V,2 GND = 0 V, RL = 2 k⍀, CL = 100 pF
to GND. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version
B Version Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
12
Relative Accuracy3
±1
± 1/2
Differential Nonlinearity3
± 0.9
± 0.9
Bipolar Zero Error3
±6
±6
Full-Scale Error3
±8
±8
Full-Scale Temperature Coefficient4 ± 30
± 30
DIGITAL INPUTS
Input High Voltage, VINH
2.4
2.4
Input Low Voltage, VINL
0.8
0.8
Input Current
IIN
Input Capacitance4
±1
±1
8
8
ANALOG OUTPUTS
Output Voltage Range
DC Output Impedance4
±5
±5
0.5
0.5
AC CHARACTERISTICS4
Voltage Output Settling Time
Positive Full-Scale Change
10
10
Negative Full-Scale Change
10
10
Digital-to-Analog Glitch Impulse3
30
30
Digital Feedthrough3
10
10
POWER REQUIREMENTS
VDD Range
VSS Range
IDD
ISS
10.8/16.5
–10.8/–16.5
10
2
10.8/16.5
–10.8/–16.5
10
2
NOTES
1Temperature Ranges are as follows: A, B Versions: –40°C to +85°C.
2Power Supply Tolerance: A, B Versions: ± 10%.
3See Terminology.
4Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
Bits
LSB max
LSB max
LSB max
LSB max
ppm of FSR/°C typ
V min
V max
µA max
pF max
V
Ω typ
µs max
µs max
nV secs typ
nV secs typ
V min/V max
V min/V max
mA max
mA max
Guaranteed Monotonic
DAC Latch Contents 0000 0000 0000
Guaranteed By Process
VIN = 0 V to VDD
Settling Time to Within ± 1/2 LSB of Final Value
Typically 4 µs; DAC Latch 100. . .000 to 011. . .111
Typically 5 µs; DAC Latch 011. . .111 to 100. . .000
DAC Latch Contents Toggled Between All 0s and all 1s
LDAC = High
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 7 mA at Thresholds
Output Unloaded; Typically 1 mA at Thresholds
TIMING CHARACTERISTICS1, 2 (VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, GND = O V, RL = 2 k⍀, CL = 100 pF. All
Specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at 25؇C, TMIN, TMAX
(All Versions)
Unit
Conditions/Comments
t13
200
t2
15
t3
70
t4
0
t5
40
t6
0
t7
20
t8
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SYNC to SCLK Falling Edge Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figure 3.
3SCLK Mark/Space Ratio range is 40/60 to 60/40.
–2–
REV. B
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