AD7765BRUZ Ver la hoja de datos (PDF) - Analog Devices

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AD7765BRUZ

24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface

Analog Devices 

AD7765

Data Sheet

Table 8. Filter Group Delay and Settling Time in Normal Power Mode

Decimation

Rate

Filter

Computation

Delay (tMCLK)

Filter

Delay (tMCLK)

tGDMCLK ADC

Group

Delay (tMCLK)

tSYNC

OFFSET

(tMCLK)

tSYNC_FS

SYNC to

FILTER_

SETTLE

Bit (tMCLK)

128×

113

6960

7073

141

13,966

256×

443

13,608

14,051

252

27,901

Modulator

Sampling

Rate (fICLK)

MCLK/2

MCLK/2

Oversampling

Ratio (OSR)

128

256

Filter Pass

Band

ODR × 0.4

ODR × 0.4

Output

Data Rate

(ODR)

MCLK/128

MCLK/256

Table 9. Filter Group Delay and Settling Time for Low Power Mode

Decimation

Rate

Filter

Computation

Delay (tMCLK)

Filter

Delay

(tMCLK)

tGDMCLK

ADC

Group

Delay

(tMCLK)

tSYNC OFFSET

(tMCLK)

SYNC to

FILTER_

SETTLE Bit

(tMCLK)

128×

162

7008

7170

167

14,248

256×

224

13,920 14,144

277

27,926

Modulator

Sampling

Rate (fICLK)

MCLK/4

MCLK/4

Oversampling

Ratio (OSR)

64

128

Filter

Pass

Band

ODR × 0.4

ODR × 0.4

Output

Data Rate

(ODR)

MCLK/128

MCLK/256

Rev. C | Page 18 of 33

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