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AD7994-0 Datasheet PDF : 32 Pages
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AD7993/AD7994
INTERNAL REGISTER STRUCTURE
The AD7993/AD7994 contain 17 internal registers (see
Figure 25) that are used to store conversion results, high and
low conversion limits, and information to configure and control
the device. Sixteen are data registers and one is an address
pointer register.
Each data register has an address that the address pointer
register points to when communicating with it. The conversion
result register is the only data register that is read only.
ADDRESS
POINTER
REGISTER
CONVERSION
RESULT REGISTER
ALERT STATUS
REGISTER
CO NF IG UR AT IO N
RE GI ST ER
CYCLE TIMER
REGISTER
DATALOW
REGISTER CH1
DATAHIGH
REGISTER CH1
D
HYSTERESIS
REGISTER CH1
A
T
DATALOW
REGISTER CH2
A
DATAHIGH
REGISTER CH2
HYSTERESIS
REGISTER CH2
DATALOW
REGISTER CH3
DATAHIGH
REGISTER CH3
HYSTERESIS
REGISTER CH3
DATALOW
REGISTER CH4
DATAHIGH
REGISTER CH4
HYSTERESIS
REGISTER CH4
SERIAL BUS INTERFACE
SDA
SCL
Figure 25. AD7993/AD7994 Register Structure
ADDRESS POINTER REGISTER
Because it is the register to which the first data byte of every
write operation is written automatically, the address pointer
register does not have and does not require an address. The
address pointer register is an 8-bit register in which the 4 LSBs
are used as pointer bits to store an address that points to one of
the AD7993/AD7994’s data registers. The 4 MSBs are used as
command bits when operating in Mode 2 (see the Modes of
Operation section). The first byte following each write address
is the address of one of the data registers, which is stored in the
address pointer register and selects the data register to which
subsequent data bytes are written. Only the 4 LSBs of this
register are used to select a data register. On power-up, the
address pointer register contains all 0s, pointing to the
conversion result register.
Table 7. Address Pointer Register
C4 C3 C2 C1 P3
0
0
0
0
P2 P1 P0
Register Select
Table 8. AD7993/AD7994 Register Addresses
P3 P2 P1 P0 Registers
0 0 0 0 Conversion Result Register (Read)
0 0 0 1 Alert Status Register (Read/Write)
0 0 1 0 Configuration Register (Read/Write)
0 0 1 1 Cycle Timer Register (Read/Write)
0 1 0 0 DATALOW Reg CH1 (Read/Write)
0 1 0 1 DATAHIGH Reg CH1 (Read/Write)
0 1 1 0 Hysteresis Reg CH1 (Read/Write)
0 1 1 1 DATALOW Reg CH2 (Read/Write)
1 0 0 0 DATAHIGH Reg CH2 (Read/Write)
1 0 0 1 Hysteresis Reg CH2 (Read/Write)
1 0 1 0 DATALOW Reg CH3 (Read/Write)
1 0 1 1 DATAHIGH Reg CH3 (Read/Write)
1 1 0 0 Hysteresis Reg CH3 (Read/Write)
1 1 0 1 DATALOW Reg CH4 (Read/Write)
1 1 1 0 DATAHIGH Reg CH4 (Read/Write)
1 1 1 1 Hysteresis Reg CH4 (Read/Write)
Rev. 0 | Page 18 of 32
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