AD9239(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD9239 Datasheet PDF : 40 Pages
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AD9239
Table 14. Memory Map Register
Addr. Register
(Hex) Name
(MSB)
Bit 7
Chip Configuration Registers
00
chip_port_
SDO active
config (local, (not
master)
required,
ignored if
not used)
01
chip_id
(global)
02
chip_grade
(global)
Device Index and Transfer Registers
05
device_
index_A
(global)
FF
device_
update (local,
master)
ADC Functions Registers
08
modes
(local)
09
Clock
(global)
0D
test_io
(local)
0E
test_bist
(local)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default Default
Value Notes/
(Hex) Comments
LSB
Soft
first
reset
Speed grade
010 = 170
100 = 210
101 = 250
16 bit
address
(default
mode for
ADCs)
8-bit Chip ID Bits[2:0]
0x0B – AD9239 – 12-bit quad
0x18
Read
only
Read
only
ADC A ADC B
ADC C ADC D 0x0F
SW
transfer
1 = on
0 = off
(default)
0x00
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Synchro-
nously
transfers
data from
the master
shift register
to the slave.
External
PDWN
pin
function
00 = full
PDWN
(default)
01 =
standby
Reset PN
long gen
1 = on
0 = off
(default)
Reset PN
short gen
1 = on
0 = off
(default)
00 = chip run
(default)
01 = full power-down
10 = standby
11 = reset
Flex output test mode
0000 = off (normal operation)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
BIST init
1 = on
0 = off
(default)
Duty
cycle
stabilize
1 = on
(default)
0 = off
BIST
enable
1 = on
0 = off
(default)
0x00
0x01
0x00
0x00
Determines
various ge-
neric modes
of chip
operation.
Turns the
internal
duty cycle
stabilizer
on and off.
When set,
the test data
is placed on
the output
pins in place
of normal
data.
When Bit 0
is set, the
built-in self-
test function
is initiated.
Rev. 0 | Page 34 of 40
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