AD9540(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD9540 Datasheet PDF : 32 Pages
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AD9540
Table 3. 48-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3, 8, 26, 30, AGND
34, 37, 43, 49
Analog Ground.
2, 4, 7, 27, 38, AVDD
44, 48
Analog Core Supply (1.8 V).
5
IOUT
DAC Analog Output.
6
IOUT
DAC Analog Complementary Output.
9
I/O_RESET
Resets the serial port when synchronization is lost in communications but does not reset the de-
vice itself (active high). When not being used, this pin should be forced low, because it floats to the
threshold value.
10
RESET
Master RESET. Clears all accumulators and returns all registers to their default values (active high).
11, 25
DVDD
Digital Core Supply (1.8 V).
12, 24
DGND
Digital Ground.
13
SDO
Serial Data Output. Used only when device is programmed for 3-wire serial data mode.
14
SDI/O
Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in
2-wire mode, it serves as both the input and output.
15
SCLK
Serial Data Clock. Provides the clock signal for the serial data port.
16
CS
Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the
serial data clocks.
17
DVDD_I/O
Digital Interface Supply (3.3 V).
18
SYNC_OUT
Synchronization Clock Output.
19
SYNC_IN/STATUS Bidirectional Dual Function Pin. Depending on device programming, this pin is either the DDS’s
synchronization input (allows alignment of multiple subclocks), or the PLL lock detect output signal.
20
I/O_UPDATE
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
21, 22, 23
S0, S1, S2
Clock Frequency and Delay Select Pins. Specify one of eight clock frequency/delay profiles.
28
CLK1
RF Divider and Internal Clock Input.
29
CLK1
RF Divider and Internal Clock Input.
31
VCML
CML Driver Supply Pin.
32
OUT0
CML Driver Complementary Output.
33
OUT0
CML Driver Output.
35
VCP
Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from
DVDD_I/O.
36
CP
Charge Pump Output.
39
REFIN
Phase Frequency Detector Reference Input.
40
REFIN
Phase Frequency Detector Reference Complementary Input.
41
CLK2
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
42
CLK2
Phase Frequency Detector Oscillator (Feedback) Input.
45
CP_RSET
Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).
46
DRV_RSET
CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).
47
DAC_RSET
DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
NOTE: The exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the device
to function properly, the paddle must be attached to analog ground.
Rev. 0 | Page 12 of 32
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