AD9540(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

AD9540
(Rev.:Rev0)

655 MHz Low Jitter Clock Generator

Analog Devices 

AD9540

TYPICAL APPLICATION CIRCUITS

25MHz

CRYSTAL

PHASE

DETECTOR

÷M

REFIN

CHARGE

PUMP

÷N

CLK2

400MHz

VCO

AD9540

DDS DAC

CML

DRIVER

÷R

Figure 32. Dual Clock Configuration

CLOCK1

CLOCK1'

EXTERNAL

REFERENCE

PHASE

DETECTOR

÷M

REFIN

CHARGE

PUMP

÷N

CLK2

÷R

AD9540

DDS DAC

622MHz

VCO

CML

DRIVER

Figure 33. Optical Networking Clock

CLOCK1

CLOCK2

APPLICATION CIRCUIT DESCRIPTIONS

Dual Clock Configuration: AD9540 Configured in a

Dual-Clock Configuration

In this loop, M = 1, N = 16, and R = 4. The DDS tuning word is

also equals to ¼, so that the frequency of CLOCK 1’ equals the

frequency of CLOCK 1. Phase adjustments in the DDS provide

14-bit programmable rising edge delay capability of CLOCK 1’

with respect to CLOCK 1 (see Figure 32).

Optical Networking Clock: AD9540 Configured as an

Optical Networking Clock

The loop can be used to generate a 622 MHz clock for OC12.

The DDS can be programmed to output 8 kHz to serve as a base

reference for other circuits in the subsystem (see Figure 33).

Rev. 0 | Page 18 of 32

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