AD9572ACPZLVD Ver la hoja de datos (PDF) - Analog Devices
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AD9572ACPZLVD Datasheet PDF : 20 Pages
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AD9572
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
VS 2
NC 3
25M 4
VS 5
XO 6
XO 7
REFCLK 8
REFSEL 9
GND 10
PIN 1
INDICATOR
AD9572
TOP VIEW
(Not to Scale)
30 106M
29 106M
28 VS
27 FREQSEL
26 VS
25 VS
24 VS
23 33M
22 100M/125M
21 100M/125M
NOTES
1. * = SHORT TO PIN 36.
2. ** = SHORT TO PIN 14.
3. NC = NO CONNECT.
4. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO
FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
Figure 6. Pin Configuration
Table 13. Pin Function Descriptions1
Pin No.
Mnemonic
1, 10, 34
GND
2
VS
3
NC
4
25M
5
VS
6, 7
XO
8
REFCLK
9
REFSEL
11
VS
12, 13
N/A
14, 36
BYPASS2, BYPASS1
15
VS
16
VS
17
156M
18
156M
19, 21
100M/125M
20, 22
100M/125M
23
33M
24
VS
25
VS
26
VS
27
FREQSEL
28
VS
29, 31
106M
30, 32
106M
Description
Ground. Includes external paddle (EPAD).
Power Supply Connection for the 25M CMOS Buffer.
No Connect. This pin should be left floating.
CMOS 25 MHz Output.
Power Supply Connection for the Crystal Oscillator.
External 25 MHz Crystal.
25 MHz Reference Clock Input. Tie low when not in use.
Logic Input. Used to select the reference source.
Power Supply Connection for the GbE PLL.
Short to Pin 14.
These pins are for bypassing each LDO to ground with a 220 nF capacitor.
Power Supply Connection for the GbE VCO.
Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers.
LVPECL/LVDS Output at 156.25 MHz.
Complementary LVPECL/LVDS Output at 156.25 MHz.
LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping.
Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.
CMOS 33.33 MHz Output.
Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers.
Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers.
Power Supply Connection for the GbE PLL Feedback Divider.
Logic Input. Used to configure output drivers.
Power Supply Connection for the FC PLL Feedback Divider.
LVPECL/LVDS Output at 106.25 MHz.
Complementary LVPECL/LVDS Output at 106.25 MHz.
Rev. B | Page 10 of 20
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