AD9739 Ver la hoja de datos (PDF) - Analog Devices
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AD9739 Datasheet PDF : 50 Pages
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AD9739
Data Sheet
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
LVDS Input Rate
LVDS Minimum Data Valid Period, tVALID (See Figure 41)
LVDS CLOCK INPUT (DCI and SYNC_IN)2
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
Maximum Clock Rate
LVDS CLOCK OUTPUT (DCO and SYNC_OUT)3
Output Voltage High (x_P or x_N)
Output Voltage Low (x_P or x_N)
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
RO Single-Ended Mismatch
Maximum Clock Rate
Min
825
175
−175
80
1250
825
175
−175
80
625
1025
150
1150
80
625
Typ
400
−400
1.2
400
−400
1.2
200
100
Max
1575
120
344
1575
120
1375
250
1250
120
10
Unit
mV
mV
mV
Ω
pF
MSPS
ps
mV
mV
mV
Ω
pF
MHz
mV
mV
mV
mV
Ω
%
MHz
1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2 DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.
3 DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.
Rev. E | Page 6 of 50
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