AD9755AST(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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AD9755AST
(Rev.:Rev0)

12-Bit, 300 MSPS High-Speed TxDAC+® D/A Converter

Analog Devices 

As stated earlier, applications requiring input data rates below

6.25 MSPS must disable the PLL clock multiplier and provide

an external 2× reference clock. At higher data rates however,

applications already containing a low phase noise (i.e., jitter)

reference clock that is twice the input data rate should consider

disabling the PLL clock multiplier to achieve the best SNR

performance from the AD9753. Note, the SFDR performance

of the AD9753 remains unaffected with or without the PLL

clock multiplier enabled.

The effects of phase noise on the AD9753’s SNR performance

become more noticeable at higher reconstructed output fre-

quencies and signal levels. Figure 8 compares the phase noise

of a full-scale sine wave at exactly fDATA/4 at different data rates

(hence carrier frequency) with the optimum DIV1, DIV0 setting.

SNR is partly a function of the jitter generated by the clock

circuitry. As a result, any noise on PLLVDD or CLKVDD may

decrease the SNR at the output of the DAC. To minimize this

potential problem, PLLVDD and CLKVDD can be connected

to DVDD using an LC filter network similar to that shown in

Figure 9.

0

–10

–20

–30

–40

–50

–60

–70

PLL ON, fDATA = 150MSPS

–80

–90

–100

PLL OFF, fDATA = 50MSPS

–110

0

1

2

3

4

5

FREQUENCY OFFSET – MHz

Figure 8. Phase Noise of PLL Clock Multiplier at fOUT =

fDATA/4 at Different fDATA Settings with DIV0/DIV1

Optimized, Using R&S FSEA30

Spectrum Analyzer

TTL/CMOS

LOGIC

CIRCUITS

FERRITE

BEADS

100␮F

ELECT.

10-22␮F

TANT.

0.1␮F

CER.

CLKVDD

PLLVDD

CLKCOM

3.1V OR 3.3V

POWER SUPPLY

Figure 9. LC Network for Power Filtering

AD9753

DAC TIMING WITH PLL ACTIVE

As described previously in Figure 7, in PLL ACTIVE mode,

Port 1 and Port 2 input latches are updated on the rising edge

of CLK. On the same rising edge, data previously present in the

input Port 2 latch is written to the DAC output latch. The DAC

output will update after a short propagation delay (tPD).

Following the rising edge of CLK, at a time equal to half of its

period, the data in the Port 1 latch will be written to the DAC

output latch, again with a corresponding change in the DAC

output. Due to the internal PLL, the time at which the data in

the Port 1 and Port 2 input latches is written to the DAC latch

is independent of the duty cycle of CLK. When using the PLL,

the external clock can be operated at any duty cycle that

meets the specified input pulsewidth.

On the next rising edge of CLK, the cycle begins again with the

two input port latches being updated, and the DAC output latch

being updated with the current data in the Port 2 input latch.

PLL DISABLED MODE

When PLLVDD is grounded, the PLL is disabled. An external

clock must now drive the CLK inputs at the desired DAC out-

put update rate. The speed and timing of the data present at input

Ports 1 and 2 is now dependent on whether or not the AD9753

is interleaving the digital input data, or only responding to data

on a single port. Figure 10 is a functional block diagram of the

AD9753 clock control circuitry with the PLL disabled.

PLLLOCK

AD9753

CLKIN+

CLKIN–

DIFFERENTIAL-

TO-

SINGLE-ENDED

AMP

TO DAC

LATCH

CLOCK

LOGIC

(،1 OR ،2)

RESET DIV0 DIV1

TO INPUT

LATCHES

TO

INTERNAL

MUX

PLLVDD

Figure 10. Clock Circuitry with PLL Disabled

DIV0 and DIV1 no longer control the PLL, but are used to set

the control on the input mux for either interleaving or non-

interleaving the input data. The different modes for states of

DIV0 and DIV1 are given in Table II.

Table II. Input Mode for DIV0,

DIV1 Levels With PLL Disabled

Input Mode

Interleaved (2×)

Noninterleaved

Port 1 Selected

Port 2 Selected

Not Allowed

DIV1

0

0

1

1

DIV0

0

1

0

1

REV. 0

–11–

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