PIOINTEN0 (R/W)
15 14 13 12 11 10 9 8 7 6
54
32
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2006)
PIO0 – PIO7
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
ADMCF326
PIOINTEN1 (R/W)
15 14 13 12 11 10 9 8 7 6 5 4
0 000 00 00 0000
321 0
0 0 0 0 DM (0x2046)
PIO8
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PIOFLAG0 (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2007)
PIO0 – PIO7
0 = NO INTERRUPT
1 = INTERRUPT FLAGGED
PIOFLAG1 (R)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2047)
PIO8
0 = NO INTERRUPT
1 = INTERRUPT FLAGGED
Figure 23. Configuration of Additional PIO Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B
–29–