ADN2849 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADN2849 Datasheet PDF : 17 Pages
| |||
Preliminary Technical Data
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 31 shows the typical application circuit for the
ADN2849. Applying DC voltages to the BIAS_SET and
MOD_SET pins can control the Modulation and bias offset
voltages. The data signal source must be connected to the
DATAP and DATAN pins using 50Ω impedance transmission
lines. If a reference clock signal is available, the retiming option
can be enabled using the CLK_SELB input. Note that the
connection between the clock signal source and
ADN2849
the CLKP and CLKN pins must be made using
50Ω transmission lines. The cross point can be adjusted using
the potentiometer R3. The modulation voltage can be enabled
or disabled using the MOD_ENB pin.
The ADN2849 can operate with positive or negative (5.0V or
5.2V) supply voltage. Care should be taken to connect the GND
pins to the positive rail of the supply voltage while the VEE and
the exposed pad to the negative rail of the supply voltage.
GND
JP1
R4
C 15
J P2
R3 GND
GND
VEE
C18 C13
G ND
GND C1
GND
J1
J2
Z0=50Ω Z0=50Ω
GND C2 GND GND
C7
GND C3
GND
J3
Z0 =50Ω Z 0=50Ω
J4
GND C4
GND
CPAN CPAP BIAS_SET VEE GND VT ERM
GN D
VT ERM
D ATA P
D ATAN
VBB
U1
ADN2849
GN D
MODP
MODN_TE RM
CLKP
GND
CLKN
VE E
MOD_ENB CLK_SELB M OD_SE T GND GND VEE
BIAS_SE T
GND
GND
Z0 = 50 Ω
GND
C11
50Ω
EAM
-5.2V
G ND
GND
VE E
C5
C6
G ND
M OD_ENB CLK_SELB
GND C10
VEE
C12
GN D
M O D _S ET
Figure 31. Typical ADN2849 application circuit
PCB LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2849 operates,
care should be taken when designing the PCB layout in order to
obtain optimum performance. It is recommended to use
controlled impedance transmission lines for the high-speed
signal paths The length of the transmission lines must be kept
to a minimum to reduce losses and pattern dependant jitter. All
the VEE and GND pins must be connected to solid copper
planes using low inductance connections. When the
connections are made through vias, multiple vias can be
connected in parallel to reduce the parasitic inductance. The
VTERM, VBB, MODN_TERM and VEE pins must be locally
decoupled with high quality capacitors. If proper decoupling
cannot be achieved using a single capacitor, the user can use
multiple capacitors in parallel for each GND pin. A 20µF
tantalum capacitor must be used as general decoupling
capacitor for the entire module The exposed pad should be
connected to the most negative rail of the supply voltage using
filled vias so that solder does not leak through the vias during
reflow. Using filled vias under the package greatly enhances the
reliability of the connectivity of the exposed pad to the GND
plane during reflow.
Rev. Pr. G | Page 15 of 17
Share Link: 