ADN2849 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

ADN2849

10.7 Gbps Electro-Absorption Modulator Driver

Analog Devices 

ADN2849

DESIGN EXAMPLE

This section describes a design example that covers the

followings:

• Headroom calculation for the required bias offset and

modulation voltages

• Required voltage range at the BIAS_SET and

MOD_SET pins to generate the required bias offset

and modulation voltages

This design example assumes a -5.2V supply voltage, 0.5V bias

offset voltage and 2V modulation voltage.

Headroom calculations

In order to operate properly, the bias offset and modulation

voltages must satisfy the following condition:

VModulation + VBias Offset ≤ VEE − VMODP min

Assuming that VMODPmin=1.7V (see table1), the above condition

became:

2.5V ≤ 5.2 −1.7 = 3.5V

BIAS_SET voltage range

The voltage range at the BIAS_SET pin to generate 0.5V bias

offset voltage at the MODP pin can be calculated using the

BIAS_SET voltage to bias offset voltage gain specification from

table1 using the formulae:

VBIAS _ SET min

=

VBIAS OFFSET

K max

VBIAS _ SET max

=

VBIAS OFFSET

K min

Where Kmin and Kmax are the minimum and maximum values of

the BIAS_SET voltage to offset bias voltage gain from table1.

Substituting the values the BIAS_SET voltage range is 0.45V to

0.55V.

Preliminary Technical Data

MOD_SET voltage range

The voltage range at the MOD_SET pin to generate 2V bias

offset voltage at the MODP pin can be calculated using the

MOD_SET voltage to bias offset voltage gain specification from

table1 using the formulae:

VMOD _ SET min

=

VMODULATION

K max

VMOD _ SET max

=

VMODULATION

K min

Where Kmin and Kmax are the minimum and maximum values of

the MOD_SET voltage to offset bias voltage gain from table1.

Substituting the values the MOD_SET voltage range is 1.05V to

1.33V.

Rev. Pr. G | Page 16 of 17

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