ADP120-33-EVALZ Ver la hoja de datos (PDF) - Analog Devices

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ADP120-33-EVALZ

100 mA, Low Quiescent Current, CMOS Linear Regulator

Analog Devices 

ADP120

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP120 is designed for operation with small, space-saving

ceramic capacitors, but functions with most commonly used

capacitors as long as care is taken with regard to the effective

series resistance (ESR) value. The ESR of the output capacitor

affects stability of the LDO control loop. A minimum of 0.70 μF

capacitance with an ESR of 1 Ω or less is recommended to ensure

stability of the ADP120. Transient response to changes in load

current is also affected by output capacitance. Using a larger

value of output capacitance improves the transient response of

the ADP120 to large changes in load current. Figure 28 and

Figure 29 show the transient responses for output capacitance

values of 1 μF and 4.7 μF, respectively.

ILOAD

1mA TO 100mA LOAD STEP,

2.5A/µs

VOUT

VOUT = 1.8V,

CIN = COUT = 1µF

(400ns/DIV)

Figure 28. Output Transient Response, COUT = 1 μF

ILOAD

1mA TO 100mA LOAD STEP,

2.5A/µs

VOUT

VOUT = 1.8V,

CIN = COUT = 4.7µF

(400ns/DIV)

Figure 29. Output Transient Response, COUT = 4.7 μF

Input Bypass Capacitor

Connecting a 1 μF capacitor from VIN to GND reduces the cir-

cuit sensitivity to printed circuit board (PCB) layout, especially

when long input traces or high source impedance are encountered.

If greater than 1 μF of output capacitance is required, increase

the input capacitor to match it.

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP120, as

long as they meet the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary tempera-

ture range and dc bias conditions. X5R or X7R dielectrics with

a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any LDO because of their poor temperature and dc

bias characteristics.

Figure 30 depicts the capacitance vs. voltage bias characteristic

of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a capa-

citor is strongly influenced by the capacitor size and voltage rating.

In general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is about ±15% over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

MURATA PART NUMBER:

GRM155R61A105KE15

1.0

0.8

0.6

0.4

0.2

0

0

2

4

6

8

10

VOLTAGE (V)

Figure 30. Capacitance vs. Voltage Characteristic

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

(1)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielec-

tric. The tolerance of the capacitor (TOL) is assumed to be 10%,

and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 30.

Substituting these values in Equation 1 yields

CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

Rev. A | Page 12 of 20

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