ADP151AUJZ-3.3-R7(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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ADP151AUJZ-3.3-R7
(Rev.:Rev0)

Ultralow Noise,200 mA, CMOS Linear Regulator

Analog Devices 

ADP151

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VIN 1

5 VOUT

ADP151

GND 2 TOP VIEW

(Not to Scale)

EN 3

4 NC

NC = NO CONNECT

Figure 3. 5-Lead TSOT Pin Configuration

1

2

A VIN

VOUT

TOP VIEW

(Not to Scale)

B EN

GND

Figure 4. 4-Ball WLCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

TSOT WLCSP Mnemonic Description

1

A1

VIN

Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.

2

B2

GND

Ground.

3

B1

EN

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

4

N/A

NC

No Connect. Not connected internally.

5

A2

VOUT

Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.

Rev. 0 | Page 6 of 24

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