ADP3180JRU Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADP3180JRU

6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller

Analog Devices 

EN is a logic low, the DELAY pin is held at ground. After the

UVLO threshold is reached and EN is a logic high, the DELAY

capacitor is charged up with an internal 20 µA current source.

The output voltage follows the ramping voltage on the DELAY

pin, limiting the inrush current. The soft-start time depends on

the values of VID DAC and CDLY, with a secondary effect from

RDLY. Refer to the Application Information section for detailed

information on setting CDLY.

When the PWRGD threshold is reached, the soft-start cycle is

stopped and the DELAY pin is pulled up to 3 V. This ensures

that the output voltage is at the VID voltage when the PWRGD

signals to the system that the output voltage is good. If EN is

taken low or VCC drops below UVLO, the DELAY capacitor is

reset to ground to be ready for another soft-start cycle. Figure 1

shows a typical start-up sequence for the ADP3180.

ADP3180

PWRGD. If the output voltage is within the PWRGD window,

the controller resumes normal operation. However, if a short

circuit has caused the output voltage to drop below the PWRGD

threshold, a soft-start cycle is initiated.

The latch-off function can be reset either by removing and reap-

plying VCC to the ADP3180 or by pulling the EN pin low for

a short time. To disable the short circuit latch-off function, the

external resistor to ground should be left open, and a high value

(>1 MW) resistor should be connected from DELAY to VCC.

This prevents the DELAY capacitor from discharging, so the

1.8 V threshold is never reached. The resistor will have an impact

on the soft-start time because the current through it will add to

the internal 20 µA current source.

Figure 1. Start-Up Waveforms, Circuit of Figure 5.

Channel 1–PWRGD, Channel 2–VOUT,

Channel 3–High Side MOSFET VGS,

Channel 4–Low Side MOSFET VGS

Current Limit, Short Circuit, and Latch-Off Protection

The ADP3180 compares a programmable current limit set point

to the voltage from the output of the current sense amplifier. The

level of current limit is set with the resistor from the ILIMIT pin

to ground. During normal operation, the voltage on ILIMIT is

3 V. The current through the external resistor is internally scaled

to give a current limit threshold of 10.4 mV/µA. If the differ-

ence in voltage between CSREF and CSCOMP rises above the

current limit threshold, the internal current limit amplifier will

control the internal COMP voltage to maintain the average out-

put current at the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is

disconnected, and the external delay capacitor is discharged

through the external resistor. A comparator monitors the DELAY

voltage and shuts off the controller when the voltage drops below

1.8 V. The current limit latch-off delay time is therefore set by the

RC time constant discharging from 3 V to 1.8 V. The Application

Information section discusses the selection of CDLY and RDLY.

Because the controller continues to cycle the phases dur-

ing the latch-off delay time, if the short is removed before the

1.8 V threshold is reached, the controller will return to normal

operation. The recovery characteristic depends on the state of

Figure 2. Overcurrent Latch-Off Waveforms,

Circuit of Figure 4.

Channel 1–PWRGD, Channel 2–VOUT,

Channel 3–CSCOMP Pin of ADP3180,

Channel 4–High Side MOSFET VGS

During startup when the output voltage is below 200 mV, a

secondary current limit is active. This is necessary because the

voltage swing of CSCOMP cannot go below ground. This sec-

ondary current limit controls the internal COMP voltage to the

PWM comparators to 2 V. This will limit the voltage drop across

the low side MOSFETs through the current balance circuitry.

There is also an inherent per phase current limit that will protect

individual phases in the case where one or more phases may stop

functioning because of a faulty component. This limit is based on

the maximum normal mode COMP voltage.

Dynamic VID

The ADP3180 incorporates the ability to dynamically change the

VID input while the controller is running. This allows the output

voltage to change while the supply is running and supplying cur-

rent to the load. This is commonly referred to as VID on-the-fly

(OTF). A VID OTF can occur under either light load or heavy

load conditions. The processor signals the controller by changing

the VID inputs in multiple steps from the start code to the finish

code. This change can be either positive or negative.

When a VID input changes state, the ADP3180 detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time is to prevent a false code due to logic skew while the

REV. 0

–9–

Share Link: