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ADP3194

6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller

Analog Devices 

ADP3194

Figure 7. Typical Start-Up Waveforms

Channel 1: PWRGD, Channel 2: CSREF,

Channel 3: DELAY, Channel 4: COMP

CURRENT-LIMIT, SHORT-CIRCUIT, AND

LATCH-OFF PROTECTION

The ADP3194 compares a programmable current-limit setpoint

to the voltage from the output of the current sense amplifier. The

level of current limit is set with the resistor from the ILIMIT pin

to ground. During normal operation, the voltage on ILIMIT is

3 V. The current through the external resistor is internally scaled

to give a current-limit threshold of 10.4 mV/μA. If the difference in

voltage between CSREF and CSCOMP rises above the current-

limit threshold, the internal current-limit amplifier controls the

internal COMP voltage to maintain the average output current at

the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is

disconnected, and the external delay capacitor is discharged

through the external resistor. A comparator monitors the DELAY

voltage and shuts off the controller when the voltage drops below

1.8 V. The current-limit latch-off delay time is, therefore, set by the

RC time constant discharging from 3 V to 1.8 V. The Application

Information section discusses the selection of CDLY and RDLY.

Because the controller continues to cycle the phases during the

latch-off delay time, the controller returns to normal operation

if the short is removed before the 1.8 V threshold is reached.

The recovery characteristic depends on the state of PWRGD. If

the output voltage is within the PWRGD window, the controller

resumes normal operation. However, if a short circuit has caused

the output voltage to drop below the PWRGD threshold, a soft

start cycle is initiated.

The latch-off function can be reset by either removing and reap-

plying VCC to the ADP3194 or by pulling the EN pin low for a

short time. To disable the short-circuit latch-off function, the

external resistor to ground should be left open, and a high value

(>1 MΩ) resistor should be connected from DELAY to VCC.

This prevents the DELAY capacitor from discharging, so the

1.8 V threshold is never reached. The resistor has an impact on

the soft start time because the current through it adds to the

internal 20 μA current source.

During startup, when the output voltage is below 200 mV, a

secondary current limit is active. This is necessary because the

voltage swing of CSCOMP cannot go below ground. This sec-

ondary current limit controls the internal COMP voltage to the

PWM comparators to 2 V. This limits the voltage drop across

the low-side MOSFETs through the current balance circuitry.

An inherent per phase current limit protects individual phases,

if one or more phases stops functioning because of a faulty com-

ponent. This limit is based on the maximum normal mode

COMP voltage.

Figure 8. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

DYNAMIC VID

The ADP3194 has the ability to dynamically change the VID

input while the controller is running. This allows the output

voltage to change while the supply is running and supplying

current to the load. This is commonly referred to as VID OTF.

A VID OTF can occur under either light or heavy load conditions.

The processor signals the controller by changing the VID inputs

in multiple steps from the start code to the finish code. This

change can be positive or negative.

When a VID input changes state, the ADP3194 detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the six

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and crowbar blanking functions for a

minimum of 100 μs to prevent a false PWRGD or crowbar

event. Each VID change resets the internal timer.

Rev. 0 | Page 10 of 32

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