ADP3194 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADP3194 Datasheet PDF : 32 Pages
| |||
ADP3194
THEORY OF OPERATION
The ADP3194 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase
operation is important for producing the high currents and
low voltages demanded by today’s microprocessors. Handling
the high currents in a single-phase converter places high thermal
demands on the components in the system, such as the inductors
and MOSFETs.
The multimode control of the ADP3194 ensures a stable, high
performance topology for
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
• Tight load line regulation and accuracy
• High current output for up to 4-phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation for tailoring design to low cost or
high performance
STARTUP SEQUENCE
During startup, the number of operational phases and their phase
relationship is determined by the internal circuitry that monitors
the PWM outputs. Normally, the ADP3194 operate as a 4-phase
PWM controller. Grounding the PWM4 pin programs 3-phase
operation, and grounding the PWM3 pin and the PWM4 pin
programs 2-phase operation.
When the ADP3194 are enabled, the controller outputs a volt-
age on PWM3 and PWM4, which is approximately 675 mV.
An internal comparator checks each pin’s voltage vs. a threshold
of 300 mV. If the pin is grounded, it is below the threshold, and
the phase is disabled. The output resistance of the PWM pins is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pins should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval that occurs during
the first two clock cycles of the internal oscillator.
After this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed and it switches between 0 V and 5 V. If the
PWM output is grounded, it remains off. The PWM outputs are
logic-level devices intended for driving external gate drivers,
such as the ADP3120A. Because each phase is monitored inde-
pendently, operation approaching 100% duty cycle is possible.
Also, more than one output can be on at the same time for
overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3194 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the fre-
quency of the remaining phases. If PWM3 and PWM4 are
grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3194 differential sense compares a high accuracy VID
DAC and a precision reference to implement a low offset error
amplifier. This maintains a worst-case specification of ±9.5 mV
differential sensing error over their full operating output voltage
and temperature range. The output voltage is sensed between
the FB pin and the FBRTN pin. Connect FB through a resistor
to the regulation point, usually the remote sense pin of the
microprocessor. Connect FBRTN directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a minimal current of 100 μA
to allow accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
OUTPUT CURRENT SENSING
The ADP3194 provide a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element, such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system:
Output inductor DCR sensing without a thermistor for
lowest cost,
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature,
Sense resistors for highest accuracy measurements.
Rev. 0 | Page 8 of 32
Share Link: 