ADP3422 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADP3422 Datasheet PDF : 16 Pages
| |||
ADP3422–SPECIFICATIONS (continued)
Parameter
Symbol
Conditions
Min
Typ Max
Unit
LOW-SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
Output Current
VDRVLSD
IDRVLSD
DPRSLP = H
DPRSLP = L
VDRVLSD = 1.5 V
DPRSLP = L
DPRSLP = H
0.7 VCC
+0.4
–0.4
0.4
V
VCC
V
mA
mA
OVER/REVERSE VOLTAGE
PROTECTION
Over-Voltage Threshold
VCOREFB,OVP
Reverse-Voltage Threshold
VCOREFB,RVP
Output Current (Open Drain Output) ICLAMP
VCOREFB Rising
VCOREFB Falling
VCOREFB Falling
VCOREFB Rising
VCLAMP = 1.5 V
VCOREFB = 2.2 V
VCOREFB = VDACOUT = 1.25 V 1
2.0 2.2
V
1.8
V
–0.3
V
–0.05
V
10
µA
4
mA
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Two test conditions:
1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right
after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.
2. PWRGD is forced to fail (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD = 1.25 V) right after the moment that
BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.
3Guaranteed by characterization.
4Measured from 50% of VID code transition amplitude to the point where V DACOUT settles within ± 1% of its steady state value.
540 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
6Measured between the 30% and 70% points of the output voltage swing.
Specifications subject to change without notice.
–4–
REV. 0
Share Link: 