ADV7304A/ADV7305A
CLKIN_A
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t9 t10
Cb0
Y0
t12
t11
Cr0
Y1
t13
t14
Crxxx
Yxxx
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 6. PS 4:2:2 1 ϫ 10-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input
Mode at Subaddress 01h = 111)
CLKIN_A
t9 t10
t12
CONTROL
I/PS
S_HSYNC,
S_VSYNC,
S_BLANK
IN SLAVE
MODE
S9–S2
Cb
Y
Cr
Y
Cb
Y
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t11
t13
t14
IN MASTER/SLAVE
MODE WITH
EAV/SAV
Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)
–8–
REV. A