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AN217

C8051F35X DELTA-SIGMA ADC USER’SGUIDE

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AN217

SFR Definition 2.5. ADC0MD: ADC0 Mode

R/W

AD0EN

Bit7

R

R/W

R/W

R

-

Reserved Reserved

-

Bit6

Bit5

Bit4

Bit3

R/W

R/W

R/W

Reset Value

AD0SM

00000000

Bit2

Bit1

Bit0

SFR Address: 0xF3

Bit 7: AD0EN: ADC0 Enable Bit.

0: ADC0 Disabled. ADC is in low-power shutdown.

1: ADC0 Enabled. ADC is active and ready to perform calibrations or conversions.

Note: Disabling the ADC automatically resets the AD0SM bits back to the “Idle” state.

Bit 6: Unused: Read = 0b, Write = don’t care.

Bits 5–4: RESERVED: Must Write to 00b.

Bit 3: Unused: Read = 0b, Write = don’t care.

Bits 2–0: AD0SM: ADC0 System Mode Select.

These bits define the operating mode for the ADC. They are used to initiate all ADC conversion and

calibration cycles.

000: Idle

001: Full Internal Calibration (offset and gain).

010: Single Conversion.

011: Continuous Conversion.

100: Internal Offset Calibration.

101: Internal Gain Calibration.

110: System Offset Calibration.

111: System Gain Calibration.

Note: Any system mode change by the user during a conversion or calibration will termi-

nate the operation, and corrupt the result. To write to many of the other ADC registers, the

AD0SM bits must be set to IDLE mode (000b).

10

Rev. 0.2

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