AT17C010A-10PC Ver la hoja de datos (PDF) - Atmel Corporation

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AT17C010A-10PC

FPGA Configuration EEPROM Memory

Atmel Corporation 

AT17C/LV512A/010A

Figure 1. Configuration with a Single AT17A Series Configurator(1)(2)(3)

VCC

VCC

VCC

1 kW

1 kW

1 kW

0.1 mF

EPF6K/EPF10K

nCONFIG

DCLK

DATA0

nCE CONF_DONE

MSEL0

nSTATUS

MSEL1

VCC

AT17C512A/010A/020A

AT17LV512A/010A/020A

DCLK

SER_EN

DATA

nCS

OE

READY

GND

Notes:

1. The use of the READY pin is optional for the 20-lead PLCC and the 32-lead TQFP packages. The 8-lead PDIP package

does not have a READY pin.

2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before

configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)

3. Reset polarity of EEPROM must be set active Low (OE active High)

5

0974E–08/01

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