AT52BC6402AT Ver la hoja de datos (PDF) - Atmel Corporation

Número de pieza

componentes Descripción

Fabricante

AT52BC6402AT

64-Mbit Flash, 16-Mbit PSRAM (x16 I/O)

Atmel Corporation 

AT52BC6402A(T)

Timing Diagrams

Power-up Sequence Timing

VCC

CS2

Wait 200 µs

Normal Operation

CS1

Note: Power-up time is defined when CS2 is kept high before VCC reaches specified minimum level. In case of CS2 is switched from

low level to high level, after VCC reached specified level, it is defined as the deep power-down exit.

Deep Power-down Entry/Exit Sequence Timing

Suspend

1 µs Deep Power-down Mode

CS2

Wait 200 µs

Normal Operation

CS1

Note: When switching CS2 from high level to low level, the device will be in the deep power-down. In this case, an internal refresh

stops and the data might be lost.

Standby Mode Characteristics Timing

tRC

Standby Mode

CS1

ISB1

Deep Power-down Mode Characteristics Timing

Suspend 1 µs

CS2

Deep Power-down Mode

IDPD

31

3441B–STKD–11/04

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