AT52BC6402AT Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
AT52BC6402AT Datasheet PDF : 38 Pages
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AT52BC6402A(T)
Write Cycle 1 (PSWE Controlled)(1),(4),(5),(9),(10)
tWC
ADDRESS
tCW
CS1
tWR(2)
CS2
VIH
UB,LB
PSWE
tAS
DATA IN HIGH-Z
DATA OUT
tAW
tBW
tWP
tDW
tWHZ(3)(8)
DATA VALID
tDH
tOW
(6)
(7)
Write Cycle 2 (CS1 Controlled)(1),(4),(5),(9),(10)
tWC
ADDRESS
tAS
tCW
CS1
tWR(2)
CS2
VIH
UB, LB
PSWE
DATA IN HIGH-Z
tAW
tBW
tWP
tDW
tDH
DATA VALID
DATA OUT HIGH-Z
Notes:
1. A write occurs during the overlap of a low CS1, a low PSWE, and a low UB or LB.
2. tWR is measured from the earlier of CS1 or PSWE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the CS1, LB and UB low transition occur simultaneously with the PSWE low transition or after the PSWE transition, out-
puts remain in a high impedance state.
5. PSOE is continuously low (PSOE = VIL).
6. Q (data out) is the invalid data.
7. Q (data out) is the read data of the next address.
8. The tWHZ is defined as the time at which the outputs achieves the high impedance state. It is not referenced to output voltage
levels.
9. CS1 in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
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3441B–STKD–11/04
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