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XRD9812

3-Channel 10/12-Bit Linear CCD & CIS Sensor Signal Processors

Exar Corporation 

XRD9810/12

3-Channel CIS/Sample and Hold Mode

The XRD9810/12 also supports operation for Contact

Image Sensor (CIS) and S/H applications.

Channel synchronization occurs when the rising edge of

ADCCLK samples a logic 0 on the SYNCH input. The Red

channel is always digitized first following synchronization

and will be selected as long as the rising edge of ADCCLK

samples a logic 0 on the SYNCH input. For DC-coupled

inputs the reference clamp and input buffer should be

disabled and input polarity should be set to 1

(non-inverting). In this mode of operation the BSAMP

input is connected to DGND and input sampling occurs on

the falling edge of VSAMP.

When using AC coupled inputs the coupling capacitor

must be clamped to the required common-mode input

voltage when the signal source output is at a reference

level. This can be accomplished by enabling the S/H Line

clamp mode in configuration register 1 and clamping the

input capacitor to the internal clamp voltage at the

beginning of each line via the SYNCH input. The required

width of the SYNCH signal is dependent on the value of

the coupling capacitor, XRD9810/12 clamp resistance,

source output resistance and desired accuracy. This is

explained further in Coupling Capacitor Requirements. If

AC coupling is used the input buffer (configuration

register 1) must be enabled to eliminate input-bias current

errors inherent to the sampling process. The input buffer

is not required or recommended in DC coupled

applications.

1-Channel CIS/ Sample and Hold Mode

The 1-Channel CIS S/H mode allows high-speed

acquisition and processing of a single channel. The

timing, clamp and buffer configurations are similar to the

3-channel mode with the exception that VSAMP timing

option #2 is not supported. To select a single channel

input the color bits of configuration register 1 must be set

to the appropriate value. The A/D input will begin to track

the selected color input on the next positive edge of

ADCCLK. In single color mode the SYNCH signal has no

effect on synchronization but still affects clamping. (See

clamp mode). If the configuration is toggled from single

color to 3-channel mode, RGB scanning will not occur

until the circuit is resynchronized with the SYNCH pulse.

Power Supplies and Digital I/O

The XRD9810/12/20/22 utilizes separate analog and

digital power supplies. All digital I/O pins are 3V/5V

compatible and allow easy interfacing to external digital

ASICs. For single supply systems the analog and digital

supply pins can be separately connected and bypassed

to reduce noise coupling from digital to analog circuits.

Coupling Capacitor Requirements

The size of the external coupling capacitors depends on a

number of items including the clamp mode, pixel rate,

channel gain, black-level variation and system accuracy

requirements. The major limitation for each clamp mode

is shown below.

CDS Mode

S/H Mode

Pixel

Clamp

(Buffer

Disabled)

Line

Clamp

(Buffer

Enabled)

· Black level pixel-

pixel variation

· Initial charging

· Initial charging

· Capacitor droop

(common-mode

range)

Not Applicable

· Initial Charging

· Capacitor droop

(accuracy error)

Table 8. Coupling Capacitor Limitation

Maximum Capacitance (CDS Pixel Mode)

Limitation #1

Since the black-level is clamped during each pixel period

the input bias current contributes an insignificant amount

of droop during one pixel period. However, pixel-pixel

variations in the black level may appear as errors . For a

worst case gain of -10, 2V A/D FSR and 10-bit accuracy

one lsb of error corresponds to 200 V input-referred.

Assuming 2mV of pixel-pixel variation in the black level

the maximum coupling capacitor can be determined as a

function of the clamping period and internal clamp

resistance.

Rev. 1.00

19

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