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TDA10021HT

DVB-C channel receiver

Philips Electronics 

Philips Semiconductors

DVB-C channel receiver

Product specification

TDA10021HT

SYMBOL PIN TYPE(1)

DESCRIPTION

DO[7:4] 37 to 40

O data output bus: this 8-bit parallel data is the output from the TDA10021HT after

demodulation, de-interleaving, RS decoding and de-scrambling. When one of the

two possible parallel interfaces is selected (parameter SERINT = 0, index 20) then

DO[7:0] is the transport stream output. When the serial interface is selected

(parameter SERINT = 1, index 20) then the serial output is on pin DO[0].

VDDDI8

VSSD18

VDDD33

VSSD33

DO[3:0]

41

42

43

44

45 to 48

S digital supply voltage for the core (1.8 V typ.)

G digital ground for the core

S digital supply voltage for the pads (3.3 V typ.)

G digital ground for the pads

O data output bus: this 8-bit parallel data is the output from the TDA10021HT after

demodulation, de-interleaving, RS decoding and de-scrambling. When one of the

two possible parallel interfaces is selected then DO[7:0] is the transport stream

output. When the serial interface is selected then the serial output is on pin DO[0].

VSSD1

49

VDDD1

50

VSSA2

51

VDDA2

52

Vref(pos)

53

G ground return for the digital switching circuitry (ADC)

S power supply input for the digital switching circuitry 1.8 V (ADC)

G ground return for the analog clock drivers (ADC)

S power supply input for the analog clock drivers 3.3 V (ADC)

O this is a positive voltage reference for the ADC. It is derived from the internal band

gap voltage, VBG, with an on-chip fully differential amplifier.

Vref(neg)

54

O this is the negative voltage reference for the ADC. It is derived from the internal

band gap voltage, VBG, with an on-chip fully differential amplifier.

VDDA3

VSSA3

VIM

55

S power supply input for the analog circuits 3.3 V (ADC)

56

G ground return for analog circuits (ADC)

57

I negative input to the ADC: this pin is DC biased to half-supply through an internal

resistor divider (2 × 20 kΩ resistors). In order to stay in the range of the ADC,

VIP − VIM should remain between the input range corresponding to the SW

register (index 1B − default value = 0.5 V).

VIP

58

I positive input to the ADC: this pin is DC biased to half-supply through an internal

resistor divider (2 × 20 kΩ resistors). In order to stay in the range of the ADC,

VIP − VIM should remain between the input range corresponding to the SW

register (index 1B − default value = 0.5 V).

VSSA3

59

VDDA3

60

VCCD(PLL)

61

DGND

62

G ground return for analog circuits (ADC)

S power supply input for the analog circuits 3.3 V (ADC)

S power supply for the PLL digital section 1.8 V

G ground connection for the PLL digital section

PLLGND

63

G ground connection for the PLL analog section

VCCA(PLL)

64

S power supply for the PLL analog section 3.3 V

Note

1. All inputs (I) are TTL, 5 V tolerant (except pins XIN, VIP and VIM). OD are open-drain outputs, so they must be

connected by a pull-up resistor to either VDDD33 or VDDD50.

2001 Oct 01

6

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