CS5181 Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Fabricante

CS5181

∆Σ Modulator & 400 kHz to 625 kHz 16-Bit ADC

Cirrus Logic 

CS5181

SDO, SDO — Serial Data Out

Serial Data Output. Output pin for 16-bit serial data word. The SDO output is the complement

of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board

layout. Output data is output in twos complement format MSB first.

FSO — Frame Sync Output

Frame Sync Output. The Frame Sync Output turns low to indicate the beginning of an output

word from the SDO pin. It returns high after the 16 data bits have been clocked out.

Control Pins

RESET — Reset and Calibration

When the RESET pin is pulled to a logic low the converter will perform a reset of its digital

logic. When the level on this pin is brought back to a logic high the chip starts normal

operation, following a two clock cycle delay period. When MODE = 1, the chip goes through

an internal gain and offset calibration routine following this reset sequence.

PWDN — Power Down Mode

A logic 0 on the PWDN pin will put the device into a power-down mode.

MODE — Modulator Only Mode

MODE is held at a logic high for normal operation. In normal operation the device utilizes the

digital decimation filter and calibration ciruitry. MODE = 0 puts the part in modulator only

mode whereby most of the digital circuitry is powered-down and the modulator bit-stream is

output from the SDO and SDO pins.

SYNC — Synchronization of Filter

The SYNC input can be used to restart the digital filter of the converter at the beginning of its

convolution cycle. The SYNC input is used to synchronize the filters of multiple converters in

a system. When the SYNC signal goes high, the filter will be initialized and will begin its

convolution cycle on the next rising edge of MCLK. If not used, tie SYNC to DGND.

MFLAG — Invalid Conversion Flag

MFLAG goes high if the modulator portion of the converter goes unstable. If MFLAG is high,

the output data from the converter may be invalid.

MCLK, MCLK — Master Clock Signal

Master clock input accepts a CMOS level clock input to the converter with worst case duty

cycle of 45-55% (typically 40 MHz). MCLK is not actually used inside the device, but can be

used for radiated noise cancellation if MCLK and MCLK are run adjacent to each other on the

PC board.

DS250PP1

17

Share Link: