CS8406
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the at-
tached device through the control registers. The following parameters are adjustable:
• Master or slave
• Serial clock frequency
• Audio data resolution
• Left or right justification of the data relative to left/right clock
• Optional one-bit cell delay of the first data bit
• Polarity of the bit clock
• Polarity of the left/right clock. (By setting the appropriate control bits, many formats are pos-
sible).
Figure 7 shows a selection of common input formats with the corresponding control bit settings.
In master mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK
input pin master clock.
In slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be
synchronous to the OMCK master clock, but the serial bit clock can be asynchronous and dis-
continuous if required. The left/right clock should be continuous, but the duty cycle can be less
than the specified typical value of 50% if enough serial clocks are present in each phase to clock
all the data bits.
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DS580F1