CY8C38 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8C38 Datasheet PDF : 100 Pages
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PRELIMINARY
PSoC®3: CY8C38 Family Data Sheet
4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
Description
Bytes
Cycles
ACALL addr11
Absolute subroutine call
2
4
LCALL addr16
Long subroutine call
3
4
RET
Return from subroutine
1
4
RETI
Return from interrupt
1
4
AJMP addr11
Absolute jump
2
3
LJMP addr16
Long jump
3
4
SJMP rel
Short jump (relative address)
2
3
JMP @A + DPTR
Jump indirect relative to DPTR
1
5
JZ rel
Jump if accumulator is zero
2
4
JNZ rel
Jump if accumulator is nonzero
2
4
CJNE A,Direct, rel
Compare direct byte to accumulator and jump if not equal
3
5
CJNE A, #data, rel
Compare immediate data to accumulator and jump if not equal
3
4
CJNE Rn, #data, rel
Compare immediate data to register and jump if not equal
3
4
CJNE @Ri, #data, rel
Compare immediate data to indirect RAM and jump if not equal
3
5
DJNZ Rn,rel
Decrement register and jump if not zero
2
4
DJNZ Direct, rel
Decrement direct byte and jump if not zero
3
5
NOP
No operation
1
1
4.4 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
„ A central hub that includes the DMA controller, arbiter, and
router
„ Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
„ CPU and DMA controller are both bus masters to the PHUB
„ Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
„ Simultaneous CPU and DMA access to peripherals located on
different spokes
„ Simultaneous DMA source and destination burst transactions
on different spokes
„ Supports 8, 16, 24, and 32-bit addressing and data
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, CAN, I2C, Timers, Counters, and PWMs
5
DFB
6
UDBs group 1
7
UDBs group 2
Document Number: 001-11729 Rev. *I
Page 15 of 100
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