DS1610 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1610

Partitioned NV Controller

Dallas Semiconductor -> Maxim Integrated 

DS1610

OPERATION - DISABLE PIN CONNECTED TO VCCO

The DS1610 performs five circuit functions required to battery backup a RAM. First, a switch is provided

to direct power from the battery or the incoming power supply (VCCI) depending on which is greater. This

switch has a voltage drop of less than 0.2 volts. The second function provided by the DS1610 is power-

fail detection. The incoming supply (VCCI) is constantly monitored. When the supply goes out of

tolerance a precision comparator detects power failure and inhibits both the chip enable output ( CEO ) and

the write enable output ( WEO ). A third function of write protection is accomplished by holding both the

chip enable output CEO and write enable output WEO to within 0.2 volts of VCCO when VCCI is out of

tolerance. If CEI is low at the time that power-fail detection occurs the CEO signal is kept low until CEI

is brought high again. However, CEO is forced high after 1.5 µs regardless of the state of CEI . Similarly,

if WEI is low at the time that power fail detection occurs, the WEO signal will remain low until WEI is

brought high or 1.5 µs elapses. The delay of write protection until the current memory cycle is complete

prevents corrupted data. Power-fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance

pin TOL grounded. If the tolerance pin is connected to VCCO then power-fail detection occurs in the range

of 4.5 volts to 4.25 volts. The PF0 signal is driven low and remains low until VCCI returns to nominal

conditions. During nominal supply conditions CEO will follow CEI and WEO will follow WEI . The

fourth function which the DS1610 performs is a battery status warning so that potential data loss is

avoided. Each time VCCI is applied to the device battery status is checked with a precision comparator. If

during battery backup no switch occurred from one battery to the other, the voltage of the battery

supplying power when VCCI is applied is checked. If this voltage is less than 2.0 volts the second chip

enable cycle after power is applied is inhibited. If any switch from one battery to another did occur the

voltage of both batteries is checked. If either voltage is less than 2.0 volts the second chip enable cycle

will be inhibited. Battery status can therefore be determined by performing a read cycle after power up to

any location in memory, verifying that memory location’s contents. A subsequent write cycle can then be

executed to the same memory location altering the data. If the next read cycle fails to verify the written

data then the data is in danger of being corrupted. The fifth function of the DS1610 provides for battery

redundancy. When data integrity is extremely important it is wise to use two batteries to insure reliability.

The DS1610 controller provides an internal isolation switch which allows the connection of two batteries.

When entering battery backup operation, the battery with the highest voltage is selected for use. If one

battery should fail, the other would then supply energy to the connected load. The switch to a redundant

battery is transparent to circuit operation and to the user. In applications where battery redundancy is not

a major concern a single battery should be connected to the BAT1 pin. The BAT2 battery pin must be

grounded. When batteries are first connected to one or both of the VBAT pins VCCO will not show the

battery potential until VCCI is applied and removed for the first time.

OPERATION - WRITE PROTECTION PROGRAMMING MODE

When the disable pin is connected to VCCI or VCCO, the DS1610 performs all of the functions described

earlier with the addition of a partition switch which selectively write protects blocks of memory. The state

of the DIS pin is strobed and latched as VCCI crosses the power-fail trip point so that the DS1610

maintains its configuration during power loss. If the strobed value of DIS is a high the internal pulldown

resistor on the DIS pin will be disconnected in the power-fail state to eliminate the possibility of battery

discharge. The register controlling the partition switch is selected by recognition of a specific binary

pattern which is sent on address lines AW -AZ. These address lines are normally the four upper order

address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern

as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will

reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21st through 24th read

cycle will load the partition switch. Since there are 16 possible write protected partitions, the size of each

partition is determined by the size of the memory. For example, a 128k X 8 memory would be divided

into 16 partitions of 128k/16 or 8k X 8. Each partition is represented by one of the 16 bits contained in the

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