DS1610 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1610 Datasheet PDF : 10 Pages
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DS1610
21st through 24th read cycle as defined by AW through AZ and shown in Table 2. A logical 1 in a bit
location sets that partition to write protect. A logical 0 in a bit location disables write protection. For
example, if during the pattern match sequence bit 22 on address pin AX were a 1, this would cause the
partition register location for partition 5 to be set to a 1. This in turn would cause the DS1610 to inhibit
WEO from going low as WEI goes low whenever AZAYAXAW=0101. Note that while setting the partition
register, data which is being accessed from the RAM should be ignored as the purpose of the 24 read
cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that on
initial battery attach the partition register can power-up in any state.
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AW 1 0 1 1 1 1 0 0 1 1
1
0
0
0
0
0
1
1
0
1
XXXX
AX 1 1 1 1 1 0 0 1 1 1
0
0
1
0
1
1
0
0
0
0
XXXX
AY 1 1 1 1 0 0 1 1 1 0
0
1
0
1
0
1
0
0
0
1
XXXX
AZ 1 1 0 0 0 1 1 1 0 0
1
0
0
0
1
0
1
0
0
0
XXXX
PARTITION REGISTER MAPPING Table 2
Address Bit number in pattern
Partition Number
Pin
Match sequence
AW
BIT 21
AX
BIT 21
PARTITION 0
PARTITION 1
AY
BIT 21
AZ
BIT 21
PARTITION 2
PARTITION 3
AW
BIT 22
PARTITION 4
AX
BIT 22
PARTITION 5
AY
BIT 22
PARTITION 6
AZ
BIT 22
AW
BIT 23
PARTITION 7
PARTITION 8
AX
BIT 23
AY
BIT 23
PARTITION 9
PARTITION 10
AZ
BIT 23
PARTITION 11
AW
BIT 24
PARTITION 12
AX
BIT 24
PARTITION 13
AY
BIT 24
PARTITION 14
AZ
BIT 24
PARTITION 15
Address State Affected
(AZ AY AX AW)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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