EM636327 Ver la hoja de datos (PDF) - Etron Technology

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Fabricante

EM636327

512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

Etron Technology 

EtronTech

EM636327

Commands

1 BankActivate & Masked Write Disable command

(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A9 = Row Address)

The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.

By latching the row address on A0 to A9 at the time of this command, the selected row access is

initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.)

from the time of bank activation. A subsequent BankActivate command to a different row in the

same bank can only be issued after the previous active row has been precharged (refer to the

following figure). The minimum time interval between successive BankActivate commands to the

same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and

shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back

activation of both banks. tRRD(min.) specifies the minimum time required between activating

different banks. After this command is used, the Write command and the Block Write command

perform the no mask write operation.

T0

T1

T2

T3

Tn+3

Tn+4

Tn+5

Tn+6

CLK

..............

ADDRESS

C OM M A ND

Bank A

Row Addr.

RAS# - CAS# delay (tRCD)

Bank A

Activate

NOP

NOP

Bank A

Col Addr.

..............

Bank B

Row Addr.

Bank A

Row Addr.

RAS# - RAS# delay time (tRRD)

R/W A with

AutoPrecharge

..............

RAS# Cycle time (tRC)

Bank B

Activate

NOP

NOP

Bank A

Activate

: "H" or "L"

AutoPrecharge

Begin

BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)

2 BankActivate & Masked Write Enable command (refer to the above figure)

(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A9 = Row Address)

The BankActivate command activates the idle bank designated by BS signal. After this

command is performed, the Write command and the Block Write command perform the masked

write operation. In the masked write and the masked block write functions, the I/O mask data that

was stored in the write mask register is used.

3 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A8 = Don't care)

The BankPrecharge command precharges the bank disignated by BS signal. The precharged

bank is switched from the active state to the idle state. This command can be asserted anytime after

tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed

in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle

state and is ready to be activated again.

4 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A9 = "H", A0-A8 = Don't care)

The PrechargeAll command precharges both banks simultaneously and can be issued even if

both banks are not in the active state. Both banks are then switched to the idle state.

5 Read command

(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is

issued. During read bursts, the valid data-out element from the starting column address will be

available following the CAS# latency after the issue of the Read command. Each subsequent data-

out element will be valid by the next positive clock edge (refer to the following figure). The DQs go

Preliminary

6

December 1998

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