FAN6756 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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FAN6756 Datasheet PDF : 18 Pages
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Protections
FAN6756 provides full protection functions, including
Overload / Open-Loop Protection (OLP), VDD Over-
Voltage Protection (OVP), Over-Temperature Protection
(OTP), and Current-Sense Short-Circuit Protection
(SSCP). SSCP is implemented as Auto-Restart Mode,
while OVP and OTP are implemented as Latch Mode
protections. OLP is Auto-Restart Mode for
FAN6756MRMY and Latch Mode for FAN6756MLMY.
When an Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD-OFF
(11 V), the protection is reset. When VDD drops further to
VDD-OLP (7 V), the internal startup circuit is enabled and
the supply current drawn from HV pin charges the hold-
up capacitor. When VDD reaches the turn-on voltage of
17 V, normal operation resumes. In this manner, auto
restart alternately enables and disables the MOSFET
switching until the abnormal condition is eliminated.
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD-OLP
(7 V), the internal startup circuit is enabled without
resetting the protection and the supply current drawn
from HV pin charges the hold-up capacitor. Since the
protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
17 V, disabling HV startup circuit. Then VDD drops again
down to 7 V. In this manner, the Latch Mode protection
alternately charges and discharges VDD until there is no
more energy delivered into HV pin. The protection is
reset when VDD drops to 4 V, which is allowed only after
power supply is unplugged from the AC line.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage from
voltage exceeding the IC voltage rating. When the VDD
voltage exceeds 24.5 V, the protection is triggered. This
protection is typically caused by an open circuit in the
secondary-side feedback network.
Over-Temperature Protection (OTP) and External
Latch Triggering
The RT pin provides adjustable Over-Temperature
Protection (OTP) and external latch triggering function.
For OTP, an NTC thermistor, RNTC, usually in series with
a resistor RA, is connected between the RT pin and
ground. The internal current source, IRT (100 µA),
introduces voltage on RT as:
VRT IRT (RNTC RA )
(5)
At high ambient temperature, RNTC decreases, reducing
VRT. When VRT is lower than VRTTH1 (1.035 V) for longer
than tD-OTP1 (14.5 ms), the protection is triggered and the
FAN6756 enters Latch Mode protection.
The OTP can be trigged by pulling down the RT pin
voltage using an opto-coupler or transistor. Once VRT is
less than VRTTH2 (0.7 V) for longer than tD-OTP2 (185 µs),
the protection is triggered and the FAN6756 enters
Latch Mode protection.
When OTP is not used, place a 100 kΩ resistor between
this pin and ground to prevent noise interference.
© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 2.0.0
Open-Loop / Overload Protection (OLP)
Because of the pulse-by-pulse current-limit capability,
the maximum peak current is limited and, therefore, the
maximum input power is also limited. If the output
consumes more than this limited maximum power, the
output voltage (VO) drops below the set voltage. Then
the currents through the opto-coupler and transistor
become virtually zero and VFB is pulled HIGH. Once VFB
is higher than VFB-OLP (4.6 V) for longer than tD-OLP
(57.5 ms), OLP is triggered. OLP is also triggered when
the feedback loop is open by soldering defect.
Sense Short-Circuit Protection (SSCP)
The FAN6756 provides safety protection for Limited
Power Source (LPS) test. When the current-sense
resistor is short circuited by a soldering defect during
production, current-sensing information is not properly
obtained, resulting in unstable power supply operation.
To protect the power supply against a short circuit across
the current-sense resistor, FAN6756 shuts down when
current sense voltage is very low; even with a relatively
large duty cycle. As shown in Figure 37, the current-
sense voltage is sampled tON-SSCP (4.55 µs) after the gate
turn-on. If the sampled voltage (VS-CS) is lower than VSSCP
for 11 consecutive switching cycles (170 µs), the
FAN6756 shuts down immediately. VSSCP varies linearly
with line voltage. At 122 V DC input, it is typically 50 mV
(VSSCP-L); at 366 V DC, it is typically 100 mV (VSSCP-H).
Figure 37. Timing Diagram of SSCP
Two-Level Under-Voltage Lockout (UVLO)
As shown in Figure 38, as long as protection is not
triggered, the turn-off threshold of VDD is fixed internally
at VUVLO (6.5 V). When a protection is triggered, the VDD
level to terminate PWM gate switching is changed to
VDD-OFF (11 V), as shown in Figure 39. When VDD drops
below VDD-OFF, the switching is terminated and the
operating current from VDD is reduced to IDD-OLP to slow
down the discharge of VDD until VDD reaches VDD-OLP.
This delays re-startup after shutdown by protection to
minimize the input power and voltage / current stress of
switching devices during a fault condition.
Figure 38. VDD UVLO at Normal Mode
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