NM27C240 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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NM27C240 Datasheet PDF : 10 Pages
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Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and VPP. VCC power supply
must be at 12.75V during the three programming modes, and must
be at 5V in the other three modes. The VCC power supply must be
at 6.5V during the three programming modes, and at 5V in the
other three modes.
Mode Selection
The modes of operation of the NM27C240 are listed in Table 1. A
single 5V power supply is required in the read mode. All inputs are
TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection
Mode
CE/
PGM
Pins
OE
VPP
VCC Outputs
Read
VIL
Output Disable X
Standby
VIH
Programming
VIL
Program
VIL
Verify
VIL
X
5.0V DOUT
VIH
X
5.0V High Z
X
X
5.0V High Z
VIH 12.75V 6.25V DIN
VIL 12.75V 6.25V DOUT
Program
Inhibit
VIH
X 12.75V 6.25V High Z
Note 15: X can be VIL or VIH.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE) is the power control and should be used for selection. Output
Enable (OE) is the output control and should be used to gate data
to the output pins, independent of the device selection. Assuming
that the addresses are stable, address access time (tACC) is equal
to the delay from CE to output (tCE). Data is available at the outputs
tOE after falling edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC - tOE.
Standby Mode
The EPROM standby mode reduces the active power dissipation
by over 99%, from 165 mW to 0.55 mW. The EPROM is placed in
the standby mode by applying a CMOS high signal to the CE input.
When in standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRI-
STATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommo-
dates this use of multiple connections. The 2-line control function
allows for:
1. the lowest possible memory power dissipation, and
2. the complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE be decoded and used as the primary device selecting
function, while OE be made a common connection to all devices
in the array and connected to the READ line from the system
control bus. This assures that all deselected memory devices are
in their low power standby modes and that the output pins are
active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the
EPROM.
Initially, and after erasure, all bits of the EPROM are in the “1’s”
state. Data is introduced by selectively programming “0’s” into the
desired bit locations. Although only “0’s” will be programmed, both
“1’s” and “0’s” can be presented in the data word. The only way to
change a “0” to a “1” is by ultraviolet light erasure.
The EPROM is in the programming mode when the VPP power
supply is at 12.75V and OE is at VIH. It is required that at least a
0.1 µF capacitor be placed across VPP, VCC to ground to suppress
spurious voltage transients which may damage the device. The
data to be programmed is applied 16 bits in parallel to the data
output pins. The levels required for the address and data inputs
are TTL.
When the address and data are stable, and active low, TTL
program pulse is applied to the PGM input. A program pulse must
be applied at each address location to be programmed. The
EPROM is programmed with the Turbo Programming Algorithm
shown in Figure 1. Each Address is programmed with a series of
50 µs pulses until it verifies good, up to a maximum of 10 pulses.
Most memory cells will program with a single 50 µs pulse. (The
standard National Semiconductor algorithm may also be used but
it will have longer programming time.)
The EPROM must not be programmed with a DC signal applied to
the PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be con-
nected together when they are programmed with the same data.
A low level TTL pulse applied to the PGM input programs the
paralleled EPROM.
Program Inhibit
Programming multiple EPROM’s in parallel with different data is
also easily accomplished. Except for CE all like inputs (including
OE and PGM) of the parallel EPROM may be common. A TTL low
level program pulse applied to an EPROM’s PGM input with CE at
VIL and VPP at 12.75V will program that EPROM. A TTL high level
CE input inhibits the other EPROM’s from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify may be
performed with VPP at 12.75V. VPP must be at VCC, except during
programming and program verify.
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