GAL20V8C-5QJ Ver la hoja de datos (PDF) - Lattice Semiconductor
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GAL20V8C-5QJ Datasheet PDF : 23 Pages
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fmax Descriptions
CLK
Specifications GAL20V8
LOGIC
ARRAY
REGISTER
CLK
ts u
tc o
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
CLK
LOGIC
ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
LOGIC
ARRAY
REGISTER
t cf
t pd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
+5V
Input Pulse Levels
Input Rise and
GAL20V8B
Fall Times
GAL20V8C
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
2 – 3ns 10% – 90%
1.5ns 10% – 90%
1.5V
1.5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
R1
FROM OUTPUT (O/Q)
UNDER TEST
R2
TEST POINT
C L*
GAL20V8B Output Load Conditions (see figure)
Test Condition
A
B Active High
Active Low
C Active High
Active Low
R1
200Ω
∞
200Ω
∞
200Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
50pF
50pF
50pF
5pF
5pF
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
GAL20V8C Output Load Conditions (see figure)
Test Condition
A
B Active High
Active Low
C Active High
Active Low
R1
200Ω
∞
200Ω
∞
200Ω
R2
200Ω
200Ω
200Ω
200Ω
200Ω
CL
50pF
50pF
50pF
5pF
5pF
15
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