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HEF4044B Datasheet PDF : 13 Pages
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NXP Semiconductors
HEF4044B
Quad R/S latch with 3-state outputs
Table 6. Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
IDD
supply current
IO = 0 A
CI
input capacitance
11. Dynamic characteristics
VDD
5V
10 V
15 V
Tamb = −40 °C Tamb = 25 °C
Min Max Min Max
-
20
-
20
-
40
-
40
-
80
-
80
-
-
-
7.5
Tamb = 85 °C Unit
Min Max
-
150 µA
-
300 µA
-
600 µA
-
- pF
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula
tPHL
HIGH to LOW
nR to nQ; see
5 V [1] 63 ns + (0.55 ns/pF)CL
propagation delay Figure 4
10 V
29 ns + (0.23 ns/pF)CL
15 V
22 ns + (0.16 ns/pF)CL
tPLH
LOW to HIGH
nS to nQ;
5 V [1] 63 ns + (0.55 ns/pF)CL
propagation delay see Figure 4
10 V
29 ns + (0.23 ns/pF)CL
15 V
22 ns + (0.16 ns/pF)CL
tt
transition time
see Figure 4
5 V [1] 10 ns + (1.00 ns/pF)CL
10 V
9 ns + (0.42 ns/pF)CL
15 V
6 ns + (0.28 ns/pF)CL
tPHZ
HIGH to OFF-state OE → nQ;
5V
propagation delay see Figure 5
10 V
15 V
tPLZ
LOW to OFF-state OE → nQ;
5V
propagation delay see Figure 5
10 V
15 V
tPZH
OFF-state to HIGH OE → nQ;
5V
propagation delay see Figure 5
10 V
15 V
tPZL
OFF-state to LOW OE → nQ;
5V
propagation delay see Figure 5
10 V
15 V
tW
pulse width
nS input LOW;
minimum width;
see Figure 4
5V
10 V
15 V
nR input LOW;
minimum width;
see Figure 4
5V
10 V
15 V
Min Typ Max Unit
-
90 185 ns
-
40
80 ns
-
30
60 ns
-
90 180 ns
-
40
80 ns
-
30
60 ns
-
60 120 ns
-
30
60 ns
-
20
40 ns
-
50 100 ns
-
30
60 ns
-
25
50 ns
-
30
60 ns
-
25
45 ns
-
20
40 ns
-
50 100 ns
-
25
50 ns
-
20
40 ns
-
50
95 ns
-
25
45 ns
-
20
35 ns
30 15 -
ns
20 10 -
ns
16
8-
ns
30 15 -
ns
20 10 -
ns
16
8-
ns
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4044B_6
Product data sheet
Rev. 06 — 11 November 2008
© NXP B.V. 2008. All rights reserved.
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